My problem is the wrong working code in my MAX 10 development board. I have a couple of calculating VHDL codes and seperately a VHDL block which is for NIOS. If I run Calculating VHDL Blocks alone, system is working perfect and if I run NIOS block alone, it is working good too but when i tried to connect these block, system is working wrong. Signals are wrong. I am connecting just 3 or 4 pio for giving just enable in VHDL to start or stop state machines in IDLE state. The most interesting thing is when i disconnect these pio and compile project, after that connect them and compile the code again, code is working perfect. The question is why the code works wrong with first connecting operation and why is it working good after disconnect and connect PIOs?
I hope i can explain my problem. Thank you.
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Would suggest to check on the timing violation for both the block mention.
And perhaps more details such as a screenshot on your qsys diagram would be helpful for us to understand the issues.