stratix III with DDR2 temination

[Altera_Forum]

hi 

my design include stratix III device with 2 ddr2 hp core. each core is facing 5 DDR2 components when 1 of the 5 is for ECC. i looked at the termination schemes in AN408 and not found my answer. im using the OCT for serial 50ohm resistor. at the DDR2 side im using ODT for parallel termination. do i need to put a parallel termination at the FPGA side also? the traces are relevantley short so there will be less returns from the line. also i want to know if i have to use SSTL-18 std . i get a lot of power consumed & disippated from the FPGA due to SSTL-18 & if i add internal Parallel resistor i get unreasonable power disspated from the FPGA (SSTL-18 adds 3W for interfacing 10 components) . parallel resistor adds another 2-3W.. its very strange..too much heat for that addition.. your help pls.. thanx

[Altera_Forum]

AN408 has been updated and is now considering also Stratix III/IV ODT. I understand from AN408 and Stratix III Device Manual, that DDR2 data lines are operated without external resistors at the bus. For the address and control lines a parallel termination (at bus end) is necessary. The DDR2 I/O standars is SSTL-18 anyway. 

 It's also meaningful to my opinion to consult memory vendor design guides, e. g. from Micron. They are usually assuming a state-of-the-art memory controller, that have ODT as Stratix III has.  Regarding your calculation of disspated power, how many data lines do you have?

[Altera_Forum]

data lane : 16 DQ + LDM +UDM +UDQS + LDQS = 20 * 10 = 200 

running on 150Mhz clk => 300 Mhz data rate

[Altera_Forum]

The highest contribution to power losses is from activated dynamic OCT, 16 mW per DQ/DQS pin. Driving the input from 50 ohm adds 4 mW at both ends, each.

[Altera_Forum]

thats ok but where does the OE & Toggle rate take affect? 

if i entered 50% OE so the PU is effective 50% of the time so 16mWX170X0.5 DQ/DQS lines take = 1360mW. the rest of the time there is a Rs on the line so 4mWX170X0.5=340mW. thats adds to 1700mW . and what about toggle rate? the termination takes less power when u reduce the toggle rate... if i enter these specification to the EPE i get much more power (about 5 W more when i choose SSTL-18 with Rs and PU.) maybe i shouldnt choose PU? altera PDF that comes with the EPE is not clear & does not specify exactly..

[Altera_Forum]

I didn't use Altera power calculation tools with DDR2 RAM and don't know about their algorithms. I also can't say, if the results are matching real life behaviour. 

 P.S.: My real life measurements are: - Arria GX (no dynamic OCT) - SSTL18 Class I termination (optional DQ/DQS Class II termination unused) - 2GB SODIMM (64 bit)  - 400 MHz data rate - Continuous memory test with 128x4 read and write burst (near 100 % duty cycle)  2.05 A/1.8V total power consumption (VCCIO, RAM and LP2997 termination regulator)  with individual 1x4 bursts (arbitary access), the supply current reduces to 1.45 A  With Stratix III dynamic OCT, some additional power consumption of parallel termination can be expected

[Altera_Forum]

first of all thanx for the help.. 

anther Q. when when i set the stratix III for dynamic OCT does it mean Rs & Rt? the OCT implements all the termination? Rs at write & Rt at read?

[Altera_Forum]

when i enable dynamic OCT does the FGPA automatically implements Rs when writing to memory and Rt when reading from memory?? 

what termination do you recommend if i use SSTL-18 class I in a point to point data line layout ? and what about the ADD,CMD? the traces length is very short..the components are located near the fpga

[Altera_Forum]

I didn't use Stratix III yet. Rs is the serial termination, 50 ohm for SSTL class I respectively 25 ohm for SSTL class II. It can be set independantly of dynamic OCT, but I expect that both are used by default when generating a DDR2 controller by the MegaWizard. It's important to follow the instructions and also import the *.tcl files that contain these settings. 

 I would generally follow the termination scheme suggested in AN408 (updated revison of July 2008!). This means one external parallel termination at the RAM for CMD/ADDR and no external termination for DQ/DQS. With your rather slow 150 MHz clock, the design may also operate without external termination, but I won't recommend it.  There are, by the way, also specifications regarding maximal delay skew for CLK to ADDR/CMD and DQS to DQ.

[Altera_Forum]

should i use a special component for the VTT power to these RTT resistors (on the ADD/CMD )you recommended? 

my current design use the 1.8 VRM power rail to prouce 0.9v with accurate resistors..

[Altera_Forum]

Well, the VTT power should be low impedance, both DC and AC. Low AC impedance is achieved by capacitors, for low DC impedance a termination regulator as the said LP2997 is the most simple solution. Even without DQ/DQS external termination, e. g. 0.5 A may be drawn at worst case, hardly to achieve with a resistive divider or a general purpose OP.