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Honored Contributor I
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stratix IV GX70 1152 pin altlvds_rx+altpll problem

Hi, 

I am using the stratix IV evalboard (TSW1400) for testing ADC3444 from TI. 

I am running into some issues with PLL on this board. Here is what I am trying to do 

1. If I implement left/right pll (altpll) function by itself with clk8p input, it detects and implements it as PLL_R2. I can write my own code for deserialization and I don't get any errors and the project compiles with no errors and I can do testing 

2. Once I add altrvds_rx to the design (I would like to use the channel data alignment and lvds_clk rising edge options) and feed the clocks from the same left/right PLL, I can't even compile the code and fitter gives warnings 

a.can't place left/right pll in target device due to device constraints 

b.can't place in pll location pll_b1, because it doesn't accept left/right plls 

c.can't place in pll location pll_r2 due to device constraints (it was implemented in this location before adding altlvds_rx) 

d.can't place in pll location pll_t1 because the location doesn't accept left/right plls 

e.can't place in pll location pll_l2 because pll has a location assignment that is incompatible 

 

when I look at the documentation for clock network in stratix IV GX 70, 1152 pin external memory interfaces clk8p,9p,10p,11p left/right pll is pll_r2, which unfortunately is giving errors after adding altlvds_rx block 

the settings I am using are similar to the source code provided by TI for this board. TI's code compiles with no errors and shows the right location assignments. If someone has come across something similar, please let me know 

 

Thanks, 

Ramakrishna
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