CORE_nCONFIG is always triggered while doing a remote update of a stratix IV FPGA EP4SGX230 with EPCS128, which represents a reconfiguration caused by the device's logic array. It can't jump from FAC mode to APP mode.
How to fix this CORE_nCONFIG error? Thanks!
Thank you for contacting Intel community.
-Did you refer and follow the steps in Remote update userguide?
-Does below KDB related to your issue?
Thank you very much!! The above problem has been solved!
Now, a rather strange situation arises:
I now have the sof files of the three FPGA projects of FAC, APP1 and APP2, the rpd file of APP1 and the rpd file of APP2. The FAC1.jic file was generated with FAC and APP1, and the FAC2.jic file was generated with FAC and APP2.
After programming FAC1.jic, after enabling the update, it cannot jump from FAC mode to APP1 mode, power off and then power on again, and after the update is enabled, it cannot jump,too. But after transferring the rpd file of APP1, the FPGA can jump from FAC mode to APP1 mode. However, when the rpd file of APP2 is transferred and reconfigured, it cannot jump from FAC mode, and the FPGA enters an inoperable state. After power-off and then power-on, the FPGA works in FAC mode.
After programming FAC2.jic, after enabling the update, it cannot jump from FAC mode to APP2 mode, power off and then power on again, and after enabling the update, it cannot jump,too. But after transferring the rpd file of APP2, the FPGA can jump from FAC mode to APP2 mode. However, when the rpd file of APP1 is transferred and reconfigured, it cannot jump from FAC mode, and the FPGA enters an inoperable state. After powering off and then powering on, the FPGA works in FAC mode.
Half a month ago, the remote update configuration on cyclone V was successful. I have read the manual and the operation of updating the configuration remotely is the same for both models of FPGA.I have done the same procedure.
The same is that EPCS128 are used. The difference is: one is Cyclone V and one is Stratix IV. And on the Cyclone V board, the FAC and APP sof files each occupy half of the storage space, and they are not compressed. On the Stratix IV board, the FAC sof file occupies a quarter of the storage space and is compressed. The sof file of the APP project is not compressed.
What the hell is going on here?
Thank you in advance for your help！
Apologize for the delay in response.
- So, are you saying that you have Cyclone V and Stratix IV, and using EPCS flash with same setup in Quartus? but working on Cyclone V but not on Stratix IV.
- If it so, can you share to us on how you generate the .jic in convert programming file? A screenshot will also be helpful.
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