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hiii, in vhdl w/f im getting glicthes in b/w two clock cycles, im requesting you guys please give me suggestions to overcome glitches in quartus 2 vhdl coding waveforms.... !!!!!!!!!
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--- Quote Start --- hiii, in vhdl w/f im getting glicthes in b/w two clock cycles, im requesting you guys please give me suggestions to overcome glitches in quartus 2 vhdl coding waveforms.... !!!!!!!!! --- Quote End --- Clock the signal, then it will come out of a flip flop...no glitch.
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very very thank you bro......now i cleared occurring of glitches in my code......thank you once again............
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here i have another problem in the compilation, when compilation done it showing one warning as "circuit may not work properly due to clock buffer signals...." please help me to overcome this problem also.
thank you very much...........
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