system design using cyclone II

[Altera_Forum]

Hi, 

 I am trying to implement a hardware system which uses current to compute distances. The incoming current is obtained from a sensor, and will be sampled and input into my FPGA. The ADC is 14bit, 250MSPS. A lock-in amplifier will be designed within the FPGA to extract the noise from a large amount of noise.  Now my problem is: My current signal is 154KHz. When I tried to build a PLL module using the ALT_PLL megafunction, the lowest required input frequency is 10MHz...  Now I am thinking of using two PLL modules, one to divide the 10MHz into 154Khz, if that is possible, the other to create its reference signal. Am I doing the right way? Is there a better way? Also, I guess I need to build a buffer before ADC. but I dont know what type of buffer / where to get information about that. Could anyone help me? Thanks!

[Altera_Forum]

--- Quote Start ---   I am trying to implement a hardware system which uses current to compute distances. The incoming current is obtained from a sensor, and will be sampled and input into my FPGA. The ADC is 14bit, 250MSPS. A lock-in amplifier will be designed within the FPGA to extract the noise from a large amount of noise.  Now my problem is: My current signal is 154KHz. When I tried to build a PLL module using the ALT_PLL megafunction, the lowest required input frequency is 10MHz...  Now I am thinking of using two PLL modules, one to divide the 10MHz into 154Khz, if that is possible, the other to create its reference signal. Am I doing the right way? Is there a better way? Also, I guess I need to build a buffer before ADC. but I dont know what type of buffer / where to get information about that. Could anyone help me?  --- Quote End ---  What are the signal processing steps that the 'lock-in amplifier' is supposed to do? It sounds to me like you are trying to implement an analog solution (using the FPGA PLL), where a digital solution might be possible.  Why use a 250MHz ADC if your signal of interest is located at 154kHz? The analog front-end (ADC buffer) needs to be designed to pass the signal frequencies of interest, while suppressing noise outside the band you are interested in. So what are those frequencies? Does your ADC need to be 14-bits? The number of bits impacts the signal processing path data width.  If you can provide a clearer description on what you are trying to achieve is the general context of signal processing, I am sure you will get some feedback from this forum.  Cheers, Dave

[Altera_Forum]

Are you trying to build this? 

 http://en.wikipedia.org/wiki/lock-in_amplifier  What is the carrier of the signal? 154kHz?  What you need inside the FPGA is a Numerically Controller Oscillator to act as your reference sinusoid, a mixer (multiplication), and a low-pass filter. The output from the filter can be a complex-valued baseband signal from which you can obtain magnitude and phase information.  Can you control the frequency of the sinusoid you are trying to detect? Is it phase-locked to a common reference?  If so, you can phase-lock the FPGA to the same reference, generate the identical sinusoid frequency, and your digital filter output will measure the amplitude and phase of the external sinusoid.  If you do not know the frequency exactly, then you can design the NCO to have a programmable frequency and you can sweep the frequency until you find the peak at the filter output. You can also reproduce the circuit several times, measuring the response at several closely spaced frequencies. You can peak-up the system to have the center channel with the maximum value. If the sinusoid drifts, you will see the amplitude in the other channels get too large, and you can adjust the NCO frequencies appropriately.  There would be other solutions possible using FFTs and the Goertzel algorithm too (they can be implemented using IIR filters).  http://en.wikipedia.org/wiki/goertzel_algorithm  I'm sure you are not the first person to attempt to build a digital version of this lock-in amplifier. Now that you know the relevant digital terminology, you can research what people have had success with.  Cheers, Dave

[Altera_Forum]

Thx for the reply. I will try to make it clearer since I am new to hardware design... 

 The current is obtained from a position detection sensor(PSD) which transfers light into current in order to calculate the position where the light is located on the sensor. After analog processing(which is completed by another colleague), our interested signal frequency is 154Khz. Usually there are signals from other frequency bands so the noise is extremely large. That's why I wanna use a lock-in amplifier. The lock-in amplifier consists of a PLL, a mixer and a LPF. The PLL is to generate a reference signal which also is 154Khz. The locked signal and the referenced signal will be sent to the mixer and the LPF will keep the DC component of the output, which is proportional to the amplitude of the original signal of interested. The lock-in amplifier will be implemented in FPGA. There will be other DSP processing in FPGA using DSP kit, but I'm not there yet.:p About the ADC, at first I was thinking of using the Virtex 6 with AD/DA, that's where I got the information. like I said I was new to hardware design so I really don't know much about the AD/DA selection...thanks for the information.

[Altera_Forum]

Read the last page of this: 

 http://www.thinksrs.com/downloads/pdfs/catalog/sr850c.pdf  The FPGA can implement this same logic.  As I comment above, if the FPGA can also be the source of the sinusoid source, then the system design becomes a lot simpler.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---   The current is obtained from a position detection sensor(PSD) which transfers light into current in order to calculate the position where the light is located on the sensor.    --- Quote End ---  This is still not clear. You do not indicate why the light would change at 154kHz. Is the light being 'chopped'. Could you please post a diagram of your setup?    --- Quote Start ---   The lock-in amplifier consists of a PLL, a mixer and a LPF. The PLL is to generate a reference signal which also is 154Khz. The locked signal and the referenced signal will be sent to the mixer and the LPF will keep the DC component of the output, which is proportional to the amplitude of the original signal of interested.   --- Quote End ---  Right. In an FPGA, there would be a PLL, but at a much higher frequency that 154kHz. Inside the FPGA, the PLL would be used to clock a Numerically Controller Oscillator, and the output of that oscillator is a digital sinusoid and cosinusoid. One of those signals can be sent to a digital-to-analog converter (DAC) and filtered to give you a very clean 154kHz reference signal. That signal can be used to drive the sensors in your system.  The sensor output would then be sampled by an analog-to-digital coverter (ADC). The samples would then internally be multiplied by the digital versions of the NCO outputs, i.e., your samples x(t) would be demodulated by the compex-exponential exp(-j*2*pi*fo*t) = cos(2*pi*fo*t) - j*sin(2*pi*f0*t), where f0 = 154kHz, and t = n/fs, where n is the sample index and fs is the sampling frequency. The complex-valued baseband signal would then pass through two digital filters.    --- Quote Start ---    About the ADC, at first I was thinking of using the Virtex 6 with AD/DA, that's where I got the information. like I said I was new to hardware design so I really don't know much about the AD/DA selection...thanks for the information.  --- Quote End ---  You're on the wrong group if you want help with Xilinx FPGAs. However, the above description would work fine with those parts too.  For more details on FPGA signal processing read these documents: http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100paper_hawkins.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100paper_hawkins.pdf) http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100slides_hawkins.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100slides_hawkins.pdf)  Cheers, Dave

[Altera_Forum]

Thanks dave, the web described blockgram works in a similar way as I described except that I am using the ALT_PLL to build my phase locked loop. but still. how can I compromise the difference between 154Khz and the lowest required ALT_PLL frequency 10MHz?

[Altera_Forum]

--- Quote Start ---  Thanks dave, the web described blockgram works in a similar way as I described except that I am using the ALT_PLL to build my phase locked loop. but still. how can I compromise the difference between 154Khz and the lowest required ALT_PLL frequency 10MHz?  --- Quote End ---  You do not need a PLL operating at 154kHz. You need a complex-valued sinusoid operating at 154kHz. You get that using an ALT_PLL operating at 10MHz or more plus a Numerically Controller Oscillator (NCO) as provided by Altera;  http://www.altera.com/literature/ug/ug_nco.pdf  Re-read the SRS data sheet. They describe how their sinusoid is 24-bits. This means they have an NCO with 24-bits of output amplitude precision. I think the DSP blocks within the Cyclone II FPGAs can implement 9x9-bit, and 18x18-bit multiplications, so 18-bits of NCO precision would be easily handled. You need to work out your signal-to-noise requirements to determine how many bits you need in your design.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  This is still not clear. You do not indicate why the light would change at 154kHz. Is the light being 'chopped'. Could you please post a diagram of your setup?  --- Quote End ---    The light doesn't change. The light on the PSD(position sensor detector) will produce two currents I1 and I2 which decide the position of the light (X=(I1+I2)/(I1-I2), this will be performed within FPGA, right now all we want are the currents). After modulation and demodulation we get the interest current signal of 154Khz, combined with noises from other bands.     --- Quote Start ---  Right. In an FPGA, there would be a PLL, but at a much higher frequency that 154kHz. Inside the FPGA, the PLL would be used to clock a Numerically Controller Oscillator, and the output of that oscillator is a digital sinusoid and cosinusoid. One of those signals can be sent to a digital-to-analog converter (DAC) and filtered to give you a very clean 154kHz reference signal. That signal can be used to drive the sensors in your system.  The sensor output would then be sampled by an analog-to-digital coverter (ADC). The samples would then internally be multiplied by the digital versions of the NCO outputs, i.e., your samples x(t) would be demodulated by the compex-exponential exp(-j*2*pi*fo*t) = cos(2*pi*fo*t) - j*sin(2*pi*f0*t), where f0 = 154kHz, and t = n/fs, where n is the sample index and fs is the sampling frequency. The complex-valued baseband signal would then pass through two digital filters.  --- Quote End ---    I am quite confused...from my understanding, a ALT_PLL can generate a sub-frequency clock, i.e. divide the original signal frequency by 1, 2...etc. The output of PLL is a clock that is phase locked to the input signal. I would then transfer this clock into a sine wave and then multiply it with the original 154Khz signal and pass the result through a LPF. And all of the above steps will be done within FPGA. what you describe above seems more complex... or maybe I am not following...    --- Quote Start ---  You're on the wrong group if you want help with Xilinx FPGAs. However, the above description would work fine with those parts too.  --- Quote End ---   sorry if I offend anybody here... I was thinking abt using Virtex long time ago but now I am back to Cyclone II.  Thanks dave.  Allison

[Altera_Forum]

--- Quote Start ---  The light doesn't change. The light on the PSD(position sensor detector) will produce two currents I1 and I2 which decide the position of the light (X=(I1+I2)/(I1-I2), this will be performed within FPGA, right now all we want are the currents). After modulation and demodulation we get the interest current signal of 154Khz, combined with noises from other bands.    --- Quote End ---  This does not make sense. Perhaps you can post a link to the position sensor. You have not clearly described how the light is getting modulated.    --- Quote Start ---   I am quite confused...   --- Quote End ---  This is ok. You already said this is the first time you have played with hardware.    --- Quote Start ---   from my understanding, a ALT_PLL can generate a sub-frequency clock, i.e. divide the original signal frequency by 1, 2...etc. The output of PLL is a clock that is phase locked to the input signal. I would then transfer this clock into a sine wave   --- Quote End ---  Here is where you are misunderstanding how things can work in the digital world; you do not transfer the 154kHz sine wave into the analog domain to multiply by the sensor output, you sample the sensor output and take it into the digital domain, and you perform the operations there.    --- Quote Start ---   and then multiply it with the original 154Khz signal and pass the result through a LPF. And all of the above steps will be done within FPGA.   --- Quote End ---  There is no sine wave from an ALT_PLL, it is a square wave, it is a clock signal. The way you make the digital values that correspond to a stream of samples from a sine wave and a cosine wave is the NCO component clocked by the output of the PLL.  You've got the right idea, you're just a little confused on the implementation.    --- Quote Start ---   what you describe above seems more complex... or maybe I am not following...   --- Quote End ---  We're saying the same things.    --- Quote Start ---   sorry if I offend anybody here... I was thinking abt using Virtex long time ago but now I am back to Cyclone II.   --- Quote End ---  I wasn't offended, I don't care what devices you want to use :)  Cheers, Dave

[Altera_Forum]

Hi Dave, thanks for clearing up.  

 here is the link for the PSD: "en.wikipedia.org/wiki/Position_sensitive_device"  the modulation is performed in the analog domain by somebody else. I dont have a clear mind of what the process is, I can ask him if this is really important to my design.  Here is a piece of code I found on line which can transfer a clock into a sine/cosine wave  ("edaboard.com/thread39599.html"): module sine_cos(clk, reset, en, sine, cos);  input clk, reset, en;  output [7:0] sine,cos;  reg [7:0] sine_r, cos_r;  assign sine = sine_r + {cos_r[7], cos_r[7], cos_r[7], cos_r[7:3]};  assign cos = cos_r - {sine[7], sine[7], sine[7], sine[7:3]};  always@(posedge clk or negedge reset)  begin  if (!reset) begin  sine_r <= 0;  cos_r <= 120;  end else begin  if (en) begin  sine_r <= sine;  cos_r <= cos;  end  end  end endmodule // sine_cos  so, if the code works, instead of using NCO, I can transform a square wave into a sine wave right? as long as I get a 154Khz clock.  Allison

[Altera_Forum]

--- Quote Start ---   here is the link for the PSD: "en.wikipedia.org/wiki/Position_sensitive_device"   --- Quote End ---  Ok, thanks.    --- Quote Start ---   the modulation is performed in the analog domain by somebody else. I dont have a clear mind of what the process is, I can ask him if this is really important to my design.   --- Quote End ---  It is the light that is being modulated, so that you get modulated currents at the output of your sensor. The reference of the 154kHz modulation source is important, because the sensor processing needs to be synchronous with that source.    --- Quote Start ---    Here is a piece of code I found on line which can transfer a clock into a sine/cosine wave ...   --- Quote End ---  This is just a very simple NCO.    --- Quote Start ---    so, if the code works, instead of using NCO, I can transform a square wave into a sine wave right? as long as I get a 154Khz clock.   --- Quote End ---  I doubt the code will work for your application. The Altera NCO component is simple to use. You can also implement sinusoid tables using ROM. At this point, you are still trying to understand all the components in your system will fit together. So for now, just assume you will be using 'something' that creates sine and cosine samples inside the FPGA, and they will correspond to samples of a 154kHz sinusoid. The generic name for that 'something' is NCO (regardless of whether you use the NCO component from Altera).  You now need to determine how the light modulation will be synchronized to your signal processing system, so you can accurately measure the demodulated currents.  Cheers, Dave

[Altera_Forum]

Hi Dave, 

I read through the links you gave me yesterday, especially the user manual of NCO. very helpful. Thx!      --- Quote Start ---    It is the light that is being modulated, so that you get modulated currents at the output of your sensor. The reference of the 154kHz modulation source is important, because the sensor processing needs to be synchronous with that source.   --- Quote End ---    It's the current from the PSD sensor that 's been modulated. not the light. Now, let's just assume tat we can get a continuous current signal from a certain source. What we are interested is the 154Khz components in the signal.  1. suppose we decide to use a 12bit, 40MSPS ADC to perform the analog-to-digital task (about that, i searched online trying to find information about ADC filter that can suppress frequency components other than 154Khz (for example). but all i found were anti-aliasing filters. it seemed to me like when selecting an ADC, the most important thing was output bits (usually 8bit is more than enough). none of them mentioned the center frequency, like what you said yesterday. could you explain it more to me please?)  2. we need a lock-in amplifier.First I implement a PLL, which produce an output clk of 10Mhz. (btw, can this signal be locked with the 154kHz input???)  3. pass the 10Mhz clk into a NCO, which produces a 154Khz sine wave. (also, there is an optional frequency modulator function in this NCO, I read through the manual sheet, not sure if I goet what they meant. Does it say that through this function, the output sine wave can be locked with an external frequency, say, my original 154Khz signal? if so, why should I still need a PLL? if not, how can I make sure this signal is locked with my 154khz input?)  4. pass the sine wave and the original signal into a mixer.  5. use a LPF that only keeps the DC components.  sorry if I ask too much or some of them dont make sense.... i really want to make sure i understand the whole thing and am able to complete the task. Thanks for your help...  Allison

[Altera_Forum]

another thing, the minimum input for PLL is 10MHz, does it mean that I cannot use a PLL anymore?

[Altera_Forum]

--- Quote Start ---   It's the current from the PSD sensor that 's been modulated. not the light.    --- Quote End ---  Ok, thanks for the clarification.    --- Quote Start ---   Now, let's just assume tat we can get a continuous current signal from a certain source. What we are interested is the 154Khz components in the signal.  1. suppose we decide to use a 12bit, 40MSPS ADC to perform the analog-to-digital task (about that, i searched online trying to find information about ADC filter that can suppress frequency components other than 154Khz (for example). but all i found were anti-aliasing filters. it seemed to me like when selecting an ADC, the most important thing was output bits (usually 8bit is more than enough). none of them mentioned the center frequency, like what you said yesterday. could you explain it more to me please?)  2. we need a lock-in amplifier.First I implement a PLL, which produce an output clk of 10Mhz. (btw, can this signal be locked with the 154kHz input???)  3. pass the 10Mhz clk into a NCO, which produces a 154Khz sine wave. (also, there is an optional frequency modulator function in this NCO, I read through the manual sheet, not sure if I goet what they meant. Does it say that through this function, the output sine wave can be locked with an external frequency, say, my original 154Khz signal? if so, why should I still need a PLL? if not, how can I make sure this signal is locked with my 154khz input?)  4. pass the sine wave and the original signal into a mixer.  5. use a LPF that only keeps the DC components.  sorry if I ask too much or some of them dont make sense.... i really want to make sure i understand the whole thing and am able to complete the task.   --- Quote End ---  You're on the right track. Please open up the attached PDF for a block diagram of the system you would build (or at least its an initial starting point).  1. The system is coherent, i.e., there is a single master clock reference. This could be an oscillator on an FPGA board, or a synthesizer connected to a clock pin via an SMA connector on an FPGA development kit. For example, a 10MHz external reference, or say a 50MHz oscillator on a development kit. The frequency ultimately does not matter, the key here is that the system uses the same reference. For DACs and ADCs, the jitter characteristics of the reference source are critical parameters, but ignore that for now.  2. Lets assume you want to run your DAC and ADC at say 20MHz. The PLL inside the FPGA can take the reference clock and generate multiple 20MHz output signals. Two of the 20MHz signals go to the external DAC and ADC, while the other is used to clock the logic within the FPGA, i.e., your NCO clock frequency is 20MHz.  3. The numerically controlled oscillator is setup to output a 154kHz sinusoid. The in-phase (I) or cosine wave output of the NCO is sent to the DAC, and that signal is filtered to produce the 154kHz modulation reference for the current sources.  4. The multiple sensor currents are then sampled by multiple copies of the ADC circuit. The ADC samples are multiplied by the in-phase (I) and quadrature (Q, or sinewave) outputs of the NCO. This multiplication demodulates the sensor output, so that the signal of interest lies at DC.  5. The complex-baseband signal is then filtered and decimated down to a sample rate consistent with the signal-to-noise you need from each measurement. For example, if you want the estimates every 1 second, then the output sample rate is 1 second, and the filter preserves the signal with a 1Hz bandwidth (-0.5Hz to 0.5Hz). The complex-valued output can be used to estimate the magnitude and phase of the received signal (sensor output) relative to the transmitted signal (the DAC).   What you need to determine is how many bits you need in your ADC, your DAC, and your final output update rate. Alternatively, you can create a MATLAB simulation given the DAC and ADC bit-widths you have access to, quantize signals, add sensor noise, create sampled data, perform the complex-valued multiplication to baseband, filter the result, and see what you get, and then iterate.  Cheers, Dave

[Altera_Forum]

Thx Dave! 

   --- Quote Start ---   3. The numerically controlled oscillator is setup to output a 154kHz sinusoid. The in-phase (I) or cosine wave output of the NCO is sent to the DAC, and that signal is filtered to produce the 154kHz modulation reference for the current sources.  --- Quote End ---    so, this cosine wave will be sent out of FPGA to modulate the external source current, right? this ensures that the incoming current is locked with the cosine wave from NCO.      --- Quote Start ---  5. The complex-baseband signal is then filtered and decimated down to a sample rate consistent with the signal-to-noise you need from each measurement. For example, if you want the estimates every 1 second, then the output sample rate is 1 second, and the filter preserves the signal with a 1Hz bandwidth (-0.5Hz to 0.5Hz). The complex-valued output can be used to estimate the magnitude and phase of the received signal (sensor output) relative to the transmitted signal (the DAC).  --- Quote End ---    hmm...I am not sure if I get this part. so if the sampling rate of ADC is 40MSPS. to multiply the input with the cosine& sine, the clk from PLL should be 40Mhz too so the sampling rate of cosine/sine wave from NCO is 40MHz, is that correct?   and after LPF, the DC components are cos(phase) and sine(phase), if I wanna get the amplitude, mathematically it is cos^2+sine^2...and should I implement the equation in verilog to get the amplitude?  Allison

[Altera_Forum]

--- Quote Start ---   so, this cosine wave will be sent out of FPGA to modulate the external source current, right? this ensures that the incoming current is locked with the cosine wave from NCO.    --- Quote End ---  Yes.    --- Quote Start ---   hmm...I am not sure if I get this part. so if the sampling rate of ADC is 40MSPS. to multiply the input with the cosine& sine, the clk from PLL should be 40Mhz too so the sampling rate of cosine/sine wave from NCO is 40MHz, is that correct?    --- Quote End ---  You might be able to understand this a little easier if you think about this in terms of samples. Here's some MATLAB code that generates the attached PDF   % Sampling frequency fs = 40e6; % Test tone frequency f0 = 154e3; % Total sampling time T = 4/f0; % 4 periods for this example % Number of samples Nt = ceil(fs*T); % Sample index n = ; % Time index t = n/fs; % NCO output nco_i = cos(2*pi*f0*t); nco_q = sin(2*pi*f0*t); % Plot I and Q as digital looking waveforms % (you need to zoom into the figure to see the steps) figure(1) hold off stairs(n, nco_i) hold on stairs(n, nco_q, 'r') axis() What this plot shows you is the NCO output sampled in time; the samples are spaced 40MHz apart, but the signal they generate is at 154kHz. Is that clearer?  What this example does not show you is that in reality the cosine and sine would also be quantized, eg., rather than defining nco_i = cos(2*pi*f0*t), you would define a signal that can only take on say 8-bit values, i.e., nco_i = round(cos(2*pi*f0*t)*2^7);    --- Quote Start ---    and after LPF, the DC components are cos(phase) and sine(phase), if I wanna get the amplitude, mathematically it is cos^2+sine^2...and should I implement the equation in verilog to get the amplitude?   --- Quote End ---  Given the outputs of the filters output_i and output_q, the magnitude of the signal is sqrt(output_i^2 + output_q^2). You could calculate these values in Verilog, but I suspect the data update rate you require is probably pretty slow, eg. 1Hz or slower, so you can instead have your logic write the sensor values to RAM (for all the current sensor I and Q output values), and then calculate the sensor position in software.  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 I am now implementing each block unit in quartusII...  several questions: 1. the bit width got me a little confused. My input signal is 16bit, I made the NCO generate 16-bit cosine and sine wave. After mixer, I should have two modulated signals of 32bit width. Now, I keep the datapath as 32bit, and input each multiplied result into a low-pass FIR filter(developed through megafunction FIR compiler, single rate, coefficients 8bit width). Should I keep the full precision, which is 40bit length, or should I truncate MSB/LSB? from what I learnt before, the ADC has a Vref=+-2V, 16bit, then the signed fractional representation of the sampled data is (3.13), including the signed bit. I guess from NCO, the cosine & sine wave is (1.15), so after mixer it is (4.28). And after FIR the full precision is 42bit, I can keep the first 16bit if my output resolution is 16bit. right? 2. The filtered result will be squared and summed and take the root. How can I decided the bit length then?  Thanks!  Allison

[Altera_Forum]

--- Quote Start ---   I am now implementing each block unit in quartusII...   --- Quote End ---  Its not a good idea to just use Quartus. You should first design your system, eg., using MATLAB or C-code; use floating-point numbers everywhere in one model (to get an end-to-end design of an ideal system), and then create a quantized (bit-accurate) model that matches your hardware design.  In fact, its more of an iterative process. You need to first see what is available in Quartus, and then as you realize you need to understand things like bit-widths, go back to your software model and try different parameters to see how they affect your result.    --- Quote Start ---   1. My input signal is 16bit, I made the NCO generate 16-bit cosine and sine wave. After mixer, I should have two modulated signals of 32bit width.   --- Quote End ---  After the multiplication you will have two 32-bit values, however, the dynamic range of those signals will not be 32-bits. If you plot a spectrum of the input signal (or a model of it), and a spectrum of the mixer complex-valued exponential (a single tone, with harmonics), the spectrum of the mixer output is the convolution of these two signals (since they are multiplied in the time domain). The number of bits to keep is determined by where the harmonics are in this spectrum. If you want 16-bits, you might actually have to use an 18-bit NCO output value. To start with, convergent round the mixer output to 16-bits. (See the links below for an NCO example)    --- Quote Start ---   Now, I keep the datapath as 32bit, and input each multiplied result into a low-pass FIR filter(developed through megafunction FIR compiler, single rate, coefficients 8bit width). Should I keep the full precision, which is 40bit length, or should I truncate MSB/LSB?   --- Quote End ---  The number of bits to preserve depends on your signal power and the dynamic range you wish to preserve. Your filter will be coherently integrating the received sinusoid. You need to model this first to understand how the signal amplitude increases with longer filters.  Note that since you only need very narrowband filters, FIR compiler might not be your best filter type. It might be better with a combination of a CIC filter and FIR filters. For now though, just gain an understanding of how the system will plug together by starting with an FIR filter.    --- Quote Start ---   from what I learnt before, the ADC has a Vref=+-2V, 16bit, then the signed fractional representation of the sampled data is (3.13), including the signed bit. I guess from NCO, the cosine & sine wave is (1.15), so after mixer it is (4.28). And after FIR the full precision is 42bit, I can keep the first 16bit if my output resolution is 16bit. right?   --- Quote End ---  The numeric format of the input is whatever you decide it is; if your ADC input is Vpp = 2*Vp, and you conceptually normalize the input by Vp, then the input range is -1.0 to 1.0. In 16-bit format, this can be Q0.15 (sign bit and 15-bits of fraction). A 16-bit NCO output is Q0.15. The FIR filter output will depend on the number of taps.  Take a look at these slides, paper, and code examples:  http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100paper_hawkins.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100paper_hawkins.pdf) http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100slides_hawkins.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100slides_hawkins.pdf) http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc2011_fpga_dsp_code.zip (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc2011_fpga_dsp_code.zip)  Page 39 of the PDF (p38 of the slides) has an FIR filter showing input bit-widths and how they grow through the filter. p137 shows the filter again, with different parameters (the code is in the zip file).  Page 80 of the PDF (p88 of the slides) shows the spectrum of a mixer output. Note how the harmonics produce alias images. The bit width of your NCO needs to be defined to keep these alias images below the quantization noise floor of the final output bit-width.    --- Quote Start ---   2. The filtered result will be squared and summed and take the root. How can I decided the bit length then?   --- Quote End ---  I don't think you need to do that on the FPGA. Your filter will output averaged data every second or so. You need the data from all sensors to calculate a position, so start by reading them out using a processor or to MATLAB, convert the integer valued filter outputs floating-point, convert them to currents using whatever calibration scheme you come up with, and then calculate the position.  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 I did what you suggested and modeled the lock-in amplifier in matlab (floating & fixed point). The results of both are the same =). but I found several problems which I didn't expect before. 1st, 40MSPS is too high to design a good LPF if my frequency of interest is 154khz. so I adjusted the sampling frequency to 4MSPS. 2nd, the paper& slides are very helpful, thanks! but i got a lil confused about the Q0.N representation. The product of two Q0.N (actual bit is 1+0+N=N+1) number is Q0.2N (1+0+2N)? maybe it actually means Q1.2N, there are 1 signed bit, 1 bit for whole and 2N bit for fractions.  3rd, after convolution, besides LSBs, I also need to cut some MSBs too right ?  4th, I used fdatool in matlab for fixed point coeff. there is one option 'set quantized parameter' where I specify the bit width of input, coeff and output. but I still need to round the exported coeffs into fixed point integers right?  I attach my matlab code here (only the fixed point), I explained every step I did in the comments. could you please take a look and tell me if I did right? Thanks!  Allison

[Altera_Forum]

--- Quote Start ---   I did what you suggested and modeled the lock-in amplifier in matlab (floating & fixed point). The results of both are the same =).   --- Quote End ---  Great!    --- Quote Start ---   but I found several problems which I didn't expect before.   --- Quote End ---  Which is why modeling is a good way to start :)    --- Quote Start ---   1st, 40MSPS is too high to design a good LPF if my frequency of interest is 154khz. so I adjusted the sampling frequency to 4MSPS.   --- Quote End ---  Why is it too fast? You need to keep in mind that the input bandwidth to the ADC needs to be consistent with its sample rate. So if your ADC is designed to operate at 40MHz and it has an input filter with 20MHz of bandwidth, regardless of what clock rate you operate it at, it will be letting in 20MHz worth of noise. To eliminate that noise, you can either change the filter and the sample rate, or you can sample at 40MHz and then use digital decimation filters.     --- Quote Start ---    2nd, the paper& slides are very helpful, thanks! but i got a lil confused about the Q0.N representation. The product of two Q0.N (actual bit is 1+0+N=N+1) number is Q0.2N (1+0+2N)? maybe it actually means Q1.2N, there are 1 signed bit, 1 bit for whole and 2N bit for fractions.    --- Quote End ---  Qm.n representation is always signed, so there is 1-bit used for the sign, and the rest for the m and n bits, eg., a B-bit binary value can be used to a Q0.(B-1) number. The largest magnitude signed value is the most negative, eg. for an 8-bit Q0.7 value, it is the signed binary value -128, or -1.0 fractional integer. The largest product of two Q0.7 is -1 x -1 = +1, so that requires a Q1.x representation, i.e., Q0.7 x Q0.7 = Q1.14. Another way to look at it, is that an 8-bit product requires 16-bits to represent, which could potentially mean that you can use Q0.15, but because of the -1 x -1 = +1 product, the representation of the product is actually Q1.14.  If you use signed-symmetric format, where the -1.0 terms are replaced with the next most-negative value, -1.0 + 1/2^B, which is the negative of the most positive value, then the -1.0 x -1.0 = 1.0 product never occurs. The product of two Q0.7 numbers is still Q1.14 format, but you can discard the MSB (not the sign bit, but the next bit) after the product is calculated, since that bit is never set, or you can perform a multiply-add, without being concerned about the add operation causing an overflow of the MSB.    --- Quote Start ---    3rd, after convolution, besides LSBs, I also need to cut some MSBs too right ?    --- Quote End ---  It depends. If you never know what is being filtered, then you have to design for worst-case input signals. If you control the type of input signal and know what it should be (and monitor it in the hardware), then you can optimize for just the signals you expect. That is part of the modeling task :)  For example, will the sensors have amplifiers, so that the ADC input range is always driven over its full amplitude range, or will there be some minimum and maximum amplitude over which it operates? Systems with ADCs that have fewer bits will often be driven by automatic-gain control (AGC) amplifiers that keep the amplitude at the input to the ADC constant.     --- Quote Start ---    4th, I used fdatool in matlab for fixed point coeff. there is one option 'set quantized parameter' where I specify the bit width of input, coeff and output. but I still need to round the exported coeffs into fixed point integers right?   --- Quote End ---  I'm not sure about all the FDATool features. I usually just use it to calculate the filter floating-point coefficients, and then deal with the quantization of the coefficients myself.    --- Quote Start ---    I attach my matlab code here (only the fixed point), I explained every step I did in the comments. could you please take a look and tell me if I did right?  --- Quote End ---  Sure, I'll take a look.  Cheers, Dave