the link is invalid

[BQi]

https://www.intel.com/content/www/us/en/programmable/documentation/rso1586315108753.html?wapkw=Low%20Latency%20E-Tile%2040G%20Ethernet

Pls help below link

Low Latency E-Tile 40G Ethernet Intel FPGA IP User Guide

[CheePin_C_Intel]

Hi,

Sorry as I am not very clear with your specific inquiries. As I tested the following link, it seems to lead me to "Low Latency E-Tile 40G Ethernet Intel FPGA IP Release Notes". Would you mind to further elaborate on your specific issue? Thank you.

https://www.intel.com/content/www/us/en/programmable/documentation/rso1586315108753.html?wapkw=Low%20Latency%20E-Tile%2040G%20Ethernet

[BQi]

We want to get the below document, you can find it in relate information section Related Information Low Latency E-Tile 40G Ethernet Intel FPGA IP User Guide<https://www.intel.com/content/altera-www/global/en_us/index/documentation/ykb1585248146318.html#ayj1585668992814> ------- we need this document

[CheePin_C_Intel]

Hi,

Not sure if you are looking for the following:

https://www.intel.com/content/www/us/en/programmable/documentation/ocy1469823495944.html

[BQi]

In quartus 20.1, we would have two version 40GE low latency mac, one is for H tile, one is for E tile, would u pls share the E tile User guide for me? What you send to me is low latency mac for h tile, not for the e tile The link of e tile user guide is invalid.

[CheePin_C_Intel]

Hi,

As I understand it, in E-tile, we have Ethernet hard IP. To ensure we are on the same page, would you mind to further elaborate on the 40GE low latency MAC for E-Tile that you are referring to? If you are referring to a specific IP, probably some link to the IP in webpage would be helpful. You may also share with me the .ip file of the IP for better understand of the IP that you are using.

Thank you very much.

[BQi]

I don’t think it is the same document 40GE in H tile or E tile. I can not find E tile in the document. And the update date is not correct, This 40GE IP in E tile release in Apr.

[CheePin_C_Intel]

Hi,

Thanks for your update. To ensure we are on the same page, would you mind to refer me to any webpage on the 40GE IP in E-tile that you are referring to so that I could further follow up from there. You may also share with me the .ip file of the IP in your design for better understanding. Thank you very much.

[BQi]

I need the link file marked with red line

[CheePin_C_Intel]

Hi,

Sorry for the delay. Thanks for the clarification. I have had some discussion with peers on this and seems like the web link reference in the release note is broken. For your information, I have file a case to Factory to seek further clarification. I will update you by early next week or as soon as there is any valid response from them. Sorry for the inconvenience.

[CheePin_C_Intel]

Hi,

Just to update you that the Factory has fixed the link and you may try to access the user guide at the following link:

https://www.intel.com/content/www/us/en/programmable/documentation/ykb1585248146318.html