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the synthesis of a verilog program

Altera_Forum
Honored Contributor II
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hello all 

i'm trying to convert my verilog program into a design just to see the circuit how they look like, the whole compilation was successful including synthesis but i couldn't find the corresponding designed file with the gates and registers,any ideas where should i look or where should i start? i had one design before (not in verilog) and i removed it from project but when i do the technology map viewer to see the circuits i still have it ..i didn't understand why it stays there...!! 

cheers
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Altera_Forum
Honored Contributor II
471 Views

You didn't select your new design as top entity before compiling the project.

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Altera_Forum
Honored Contributor II
471 Views

thx for replying ..now i figured it out..it works now 

cheers
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