Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21615 Discussions

transient current allowed

Altera_Forum
Honored Contributor II
1,162 Views

Hi community, 

 

I have a question about the maximum allowed transient current for the different power rails. 

In the pcg on page 25 there is shown a list which contains the different power rails and the transient current and voltage ripple for each power rail. 

The voltage ripple is clear, but the transient current isn't. For VCCIO there is given a 100% transient urrent allowed for this rail? 

But 100% of what?  

 

Sorry if the solution is clear, but I don't get it. 

Please could you help me with this? 

 

Best regards! 

 

Jérôme 

 

edt: Is it correct that the percentages, I am asking about above, are referred to the Maximum Power Supply Transient Currents given in the Power Management User Guide on page 2-4 Table 2-3? 

So the table (in the PMG) states the maximum transient current when powering the device up and the percentages in the pin configuration guide on page 25 stating the max transient current (percentages) referred to the PMG during operation? 

Am I correct with my suggestion?
0 Kudos
0 Replies
Reply