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Hello,
I have a mixed-language design where I would like to instantiate a VHDL module in a Verilog file. The module has the following definition:
entity vhdl_module is
generic (
integer_values: work.vectors_and_arrays.integer_vector(7 downto 0) := (0, 0, 0, 0, 0, 0, 0, 0)
);
port(
-- list of ports
);
end vhdl_module;
The vector definition is as simple as follows:
type integer_vector is array (natural range <>) of integer;
and my instantiation is:
vhdl_module
#(
.integer_values({0,0,0,0,0,0,0,0})
)
I_vhdl_module (
//port connections
);
hat does not work and trying something like 32'd0 or 1'd0 instead of just 0 did not work any better. What I want to do is simply passing an integer value so I guess the solution must be rather simple, but I did not find it yet. By the way, the VHDL module works fine in a VHDL design where I instantiate it like that:
integer_values => (0, 0, 0, 0, 0, 0, 0, 0)
So I guess I just need to find the right way to pass an integer value...
Thanks in advance!
Regards,
javichu
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Hi Vikas,
How can I switch my verilog file to System Verilog? is there any way to define a code section as System Verilog (i.e. the module instantiation)? Thanks in advance.
Regards,
Javi
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Hi @Vicky ,
thanks for your reply. I tried that solution but I got the same error. I guess the conversion I am trying to achieve is not supported so I am thinking about a different solution... How could I pass a single integer from Verilog to a VHDL module? would it be as simplre as for example ".integer_param(5)"? then I could modify my VHDL block to get all the integer parameters separately.
Thanks again,
Javi

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