understanding avalon slave <-> master transfers

[Altera_Forum]

Hello, 

 I am trying to understand how avalon slave <-> master read and writes are working, I have seen the master and slave templates and several manuals and sheets and posts about that but I am not sure if I have understood it correctly. What I am trying to accomplish is a component which will be connected between the Nios(e) instuction master and the altera sdram controller with internal memory like a cache. For that I figured out I need a avalon slave to connect the instruction master to and a avalon master to connect to the altera sdram controller. I am also not quite sure which signals of the interfaces I really need. On the avalon slave, does the nios instruction master ever write data or does it only read it? As from my view instruction memory should be readonly but on the other hand the instructions somehow need to get into there (via the datamaster???). I figured the data width of that interface should be 32 bits as the nios instructions are also 32 bits? The address width should be the same as sdram size in bytes / 32 bits data width. So my assumption is when the instruction master wants to read an instruction it would set the address and assert the read signal on my avalon slave. The address is already cleaned from baseaddress, in the range of the sdram size, at this point ??? The avalon slave than needs to check the internal memory(cache) if valid data is there and would return it, if not it needs to read a cache block, multiple bytes, from the sdram controller, strore that internally and return the correct output. On a cache hit, I have a fixed amount of clock cycles it will take me to return the data, on a miss this will be variable depending on how long it takes the sdram controller to read and return the data. So what I would do is as soon as I see the read signal asserted, I would assert the waitrequest signal because at that point I can not know how long it will take to return valid data. As soon as I have the valid data, I would than deassert waitrequest and will "wait" until the instruction master has deasserted my slaves read signal, indicating to me that on the next clock cycle a new read could occur.  Can somebody please verify if my assumptions are correct so far?  Thanks in advance  Grobi

[Altera_Forum]

--- Quote Start ---  I am also not quite sure which signals of the interfaces I really need.  --- Quote End ---   Qsys is flexible and it allows you to define your slave and it will generate adaptation logic to make it uniform. clk,reset,address,read,readdata,waitrequest are probably all you need on the slave. On the master, you would want a bursting master.    --- Quote Start ---  On the avalon slave, does the nios instruction master ever write data or does it only read it?  --- Quote End ---   Yes, you can make a read-only interface for an instruction cache.    --- Quote Start ---  As from my view instruction memory should be readonly but on the other hand the instructions somehow need to get into there (via the datamaster???).  --- Quote End ---   Yes either through the data master of the NIOS, or maybe some other means depending on your system. For you cache, it's "dont care".    --- Quote Start ---  I figured the data width of that interface should be 32 bits as the nios instructions are also 32 bits? The address width should be the same as sdram size in bytes / 32 bits data width.  --- Quote End ---   If your SDRAM is also 32-bits, you can simplify your life and just think of it like your cache has to have the same number of address bits as the SDRAM Altera-MM Slave port does. Yes, your slave should be 32-bits just like the NIOS.     --- Quote Start ---  So my assumption is when the instruction master wants to read an instruction it would set the address and assert the read signal on my avalon slave. The address is already [cleaned from baseaddress, in the range of the sdram size, at this point ???   --- Quote End ---    Check out the "bridgesToMaster" interface property in mnl_avalon_spec.pdf  Yes, when your slave receives a read at address 0, you want your master to issue a read at address 0.    --- Quote Start ---   The avalon slave than needs to check the internal memory(cache) if valid data is there and would return it, if not it needs to read a cache block, multiple bytes, from the sdram controller, strore that internally and return the correct output. On a cache hit, I have a fixed amount of clock cycles it will take me to return the data, on a miss this will be variable depending on how long it takes the sdram controller to read and return the data. So what I would do is as soon as I see the read signal asserted, I would assert the waitrequest signal because at that point I can not know how long it will take to return valid data. As soon as I have the valid data, I would than deassert waitrequest and will "wait" until the instruction master has deasserted my slaves read signal, indicating to me that on the next clock cycle a new read could occur.  Can somebody please verify if my assumptions are correct so far?   --- Quote End ---    It all sounds roughly correct and of course there are a lot of little details you need to get correct. I'm not sure what you envision as your test and development environment, but I can recommend getting started with the Avalon BFM's in simulation sooner rather than later, but you might find using the System Console to issue reads and SignalTap to debug might be easier if you're just learning things.

[Altera_Forum]

--- Quote Start ---  It all sounds roughly correct and of course there are a lot of little details you need to get correct. I'm not sure what you envision as your test and development environment, but I can recommend getting started with the Avalon BFM's in simulation sooner rather than later, but you might find using the System Console to issue reads and SignalTap to debug might be easier if you're just learning things.  --- Quote End ---    Thank you ted for confirming that my idea of how it works is roughly correct, regarding the avalon master to read from the sdram controller :  the controller has a datawidth of 16 bits but how I understand it is that I can set a datawidth of 32 bits on the avalon master,  would set the starting address of sdram controller base address + start of the 64 byte block I want to read (that needs to be a byte alligned address, not aligned to the sdram datawidth 16 bits, right?), set a burstcount of 16 and byteenable to 4,  start via asserting avalon master read and everytime data is available from the sdram controller the readdatavaild signal would be asserted for one clock cycle.  So I just have to look for the readdatavalid signal of the sdram controller and can than read the complete 32 bit word and store it internally.  After receiving all the data I just deassert the master read signal.

[Altera_Forum]

Based on the above I put together a simple two way set associative instruction cache with 4Kb internal memory and it works in the simulator with a simple test toplevel entity but now I need to check how I can simulate this after I set it up in a qsys system.

[Altera_Forum]

--- Quote Start ---  Thank you ted for confirming that my idea of how it works is roughly correct, regarding the avalon master to read from the sdram controller :  the controller has a datawidth of 16 bits but how I understand it is that I can set a datawidth of 32 bits on the avalon master,  would set the starting address of sdram controller base address + start of the 64 byte block I want to read (that needs to be a byte alligned address, not aligned to the sdram datawidth 16 bits, right?),   --- Quote End ---   That depends on what you have set the addressUnits property in your _hw.tcl to. See mnl_avalon_spec.pdf it explains this a bit.    --- Quote Start ---   set a burstcount of 16 and byteenable to 4,    --- Quote End ---   byteenable is a bitmask so '4' won't do what you hope it would. again, see mnl_avalon_spec.pdf    --- Quote Start ---   start via asserting avalon master read and everytime data is available from the sdram controller the readdatavaild signal would be asserted for one clock cycle.  So I just have to look for the readdatavalid signal of the sdram controller and can than read the complete 32 bit word and store it internally.  After receiving all the data I just deassert the master read signal.  --- Quote End ---    The command is accepted when read=1 and waitrequest=0 for one clock period. So you would deassert read right after you saw that waitrequest hadn't been asserted. Then wait for 'readdatavalid'. After you've received the full count of 'readdatavalid' qualified transactions, the sequence is over.

[Altera_Forum]

--- Quote Start ---  Based on the above I put together a simple two way set associative instruction cache with 4Kb internal memory and it works in the simulator with a simple test toplevel entity but now I need to check how I can simulate this after I set it up in a qsys system.  --- Quote End ---    After you get this packaged into a Qsys component with a _hw.tcl file, what you want to do is to get a simulation going with the Avalon BFM's Search on here for "BFM" and you'll find threads and examples.   https://www.altera.com/support/support-resources/design-examples/design-software/simulation/exm-avalon-verification-ip.html

[Altera_Forum]

--- Quote Start ---  After you get this packaged into a Qsys component with a _hw.tcl file, what you want to do is to get a simulation going with the Avalon BFM's Search on here for "BFM" and you'll find threads and examples.   https://www.altera.com/support/support-resources/design-examples/design-software/simulation/exm-avalon-verification-ip.html  --- Quote End ---    Thank you so much ted, I really appreciate your help!   I have made those suggested changes (additional state to wait for avalon master waitrequest = 0 than setting read = 0) and now taking a good look at BFM.