Hi all,now I'm trying to generate a FIR IP CORE use the FIR COMPILER V13.0,at the step2 ,I choose to generate the Simulation Model ,finally I got the Erro INFOMATION,HERE IS the detail:Megacore Function generation error：IP functional simulation model creation failed，the following error was returned： Error：quartus ii 32-bit Analysis&Synthesis was unsuccessful .2 errors,4 warning. Actually,My QUARTUS II is 64-BIT VERSION ,AND I don't know why it would be wrong.So I need somebody who is warm-hearted to help me solve this Problem. https://alteraforum.com/forum/attachment.php?attachmentid=15171&stc=1 https://alteraforum.com/forum/attachment.php?attachmentid=15172&stc=1
Hi,Yes, we are facing the error while generating FIR in Quartus V13.0. Can you try with the Quartus version 13,1?Where we can successfully generate the required files and simulate it without any error. Attached images and transcript. Let me know if this has helped resolve the issue you are facing or if you need any further assistance. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)https://www.alteraforum.com/forum/attachment.php?attachmentid=15189 https://www.alteraforum.com/forum/attachment.php?attachmentid=15190
It’s so kind of you to help me settle this matter,which help me generate the IP core successfully.But now I encounter some new troubles.When the IP CORE was generated suscessfully,I choosed the the testbench which was generated by the fir compiler V13.1.I can show you the details.First picture shows these files in my project https://alteraforum.com/forum/attachment.php?attachmentid=15267&stc=1 which confused me is that the file-"fir_ipcore_make_bb.v" whether it should be included in my design? I remove this file from my project,and use the testbench file-‘tb_fir_ipcore_make’,the simulation tool is Modelsim-altera.when I compile my whole project,it shows the erro in‘tb_ipcore_make’,you can see it in the following picturehttps://alteraforum.com/forum/attachment.php?attachmentid=15270&stc=1 which says"Error (10481): VHDL Use Clause error at tb_fir_ipcore_make.vhd(72): design library "work" does not contain primary unit "fir_ipcore_make"",so I change the primary unit to “fir_ipcore_make_ast”,I don't know it's wrong or right,but it worked,and the compilation was successful. After I finished all of these settings and run the RTL simulatin,it noticed me there were something wrong,just as the second picture showshttps://alteraforum.com/forum/attachment.php?attachmentid=15268&stc=1 I saved this message, here it is Because I’m a beginner in FPGA design，so these things are difficult for me and I want to know what I should do.I am so sorry if I have bothered you. Thank you again. Best regards to you!
Hi,Include .qip or .qsys file generated any one of those to be included in you Quartus->files. And try to run full compile of the design. To work with ModelSim refer the msim_setup.tcl file created in project directory ../sim/mentor/msim_setup.tcl. Let me know if this has helped resolve the issue you are facing or if you need any further assistance. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)