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Valued Contributor III
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using io as clk inputs

Hi Community, 

 

is it possible to use the io s as pixelclk input? 

I dont read anything that it isnt possible. 

 

Regards 

Jérôme
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Valued Contributor III
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You can do it, but your design may suffer from clock jitters. It may result in malfunctioning of your core. 

This is NOT a good practice.
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Valued Contributor III
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Hi msj, 

 

thank you for your response. 

Do you think it will better to use the dedicated PLL / CLK inputs for such a signal? 

It helps me alot to know that it is possible. 

 

Best regards 

Jérôme
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Valued Contributor III
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Hi,  

 

I am not a pro designer but here is what i think : for example Cyclone IV handbook states that "The general I/O pins cannot drive the PLL clock input pins". This means that you will not get ability to use PLL and fine tune phase shift on your clock and probably you will fail to meet timing requirements on high speed interfaces. But if you plan to clock some low speed SDR interfaces i think it will work (I tried this and it worked).
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Valued Contributor III
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--- Quote Start ---  

Hi Community, 

 

is it possible to use the io s as pixelclk input? 

I dont read anything that it isnt possible. 

 

Regards 

Jérôme 

--- Quote End ---  

 

 

You could, but I would not recommend it. It will make life rather hard. 

Anything faster than 1-2Mhz use a dedicated clock input/pll.
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Valued Contributor III
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--- Quote Start ---  

You could, but I would not recommend it. It will make life rather hard. 

Anything faster than 1-2Mhz use a dedicated clock input/pll. 

--- Quote End ---  

 

 

Hi everyone, 

 

104MHz pclk. so pll will be the solution. Thank you everyone for the responses.  

 

Best wishes and a nice day for you all. 

Jérôme
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Valued Contributor III
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Hi Guys, 

 

If i have several pulse signals, and their rising edge is shark, how can i reserve these pulses' rising edge property when feeding them into fpga?
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Valued Contributor III
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Hi Tricky, 

 

I have one more question. 

Does it matter which CLK input (rising edge p, falling edge n) I use, or is the description only for the use as diff pair? 

I think it doesnt matter when I am using the clk inputs only for an I2C CLK or PCLK, but I will be sure that I am right with my guess. 

 

Thanks in advance 

Jérôme 

 

edt: Found it by myself I think: 

 

pcg-01018 p.2 quote from clk description : "When these clock input pins are used as single-ended pins, you can disregard the p notation." Also the other way round with the n notation . ^^  

 

Thanks Comm. :) 

 

edt2: 

Another thought about I2C CLK and PCLK. 

Will it be ok to use adjacent clk inputs as one I2C CLK and the other as PCLK? 

I2C is less than 1MHz instead of the PCLK. Will there be any strong influence of the PCLK or will it be ok? 

 

Regards. 

Jérôme
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Valued Contributor III
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Hi everyone, 

 

any quesses? 

Another thought about I2C CLK and PCLK. 

Will it be ok to use adjacent clk inputs as one I2C CLK and the other as PCLK? 

I2C is less than 1MHz instead of the PCLK. Will there be any strong influence of the PCLK or will it be ok? 

 

Regards. 

Jérôme
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Valued Contributor III
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Internally it wont be a problem - I think it will really depend what the traces do on the PCB.

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