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Valued Contributor III
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using memory Bits

Hi i wrote a vhdl design in which i wanted to buffer data like this:  

WHEN 0 => ausgangimag0 <=ausgangimag0 + resultim;ausgang2 <= ausgangimag0; 

WHEN 1 => ausgangimag1 <=ausgangimag1 + resultim;ausgang2 <= ausgangimag1; 

WHEN 2 => ausgangimag2 <=ausgangimag2 + resultim;ausgang2 <= ausgangimag2; 

WHEN 3 => ausgangimag3 <=ausgangimag3 + resultim;ausgang2 <= ausgangimag3; 

WHEN 4 => ausgangimag4 <=ausgangimag4 + resultim;ausgang2 <= ausgangimag4; .... and so on 

only much more. when i compile the design i get the error: "Error: Design contains 77634 blocks of type combinational node. However, device contains only 33216." But the memory Bits of the FPGA are empty (0 / 483840). How can i use them to buffer the data?
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Valued Contributor III
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Re: using memory Bits

Generally you have to observe the rules for RAM inference. Using the same signal for RAM read and write as in ausgangimag1 <=ausgangimag1 + resultim doesn't work I think. You should show the complete process layout for clarification.  

 

You better start from the Quartus VHDL templates.
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Valued Contributor III
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Re: using memory Bits

do you want to store it in regsiters or in RAM-cells ? 

obviously you dindt make any storage elements, so all of your assignments 

lead to a pure combinational logic
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Valued Contributor III
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Re: using memory Bits

Read this document (http://www.altera.com/literature/hb/qts/qts_qii51007.pdf) to learn how to properly infer memories in VHDL code.

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