using ram simply

[Altera_Forum]

hi everyone, 

i'm working on a basic computer architecture. i want to use a ram without any clock just read and write on it.and specially my memory is 4096*16 bit. i'm working on max plus II

[Altera_Forum]

1. Why are you using Max Plus 2, it is very old. 

2. without a clock you are going to struggle. Any reason why you are not clocking it?

[Altera_Forum]

If you want to implement the design in hardware (FPGA), you have to face the fact, that FPGA internal RAM blocks are operating synchronously, not only from Altera, also from other vendors.

[Altera_Forum]

What FPGAs are you trying to use? 

 The older FLEX10K FPGAs can operate their RAM in asynchronous mode.  MAX+Plus II is very old. If you are using an older family FPGA, you can use Quartus 9.0SP2 to build for them.  Cheers, Dave

[Altera_Forum]

Hi ssmmgg, 

 You didnt mention what kind of device you are planning to use. As others have said, your memories have to be synchronous meaning, they need clock.

[Altera_Forum]

thanks every one. 

i'm actually a computer science student. working on a basic computer from moris mano's computer architecture. it's a project.i tried to use proteus but i was not able to make components as design grows up.i tried to use max plus it does support the default symbols but i dont now how to use the memory.can any one suggest me a more simple application like max plus with custom component support and specially a simple memory.i will use it as in device memory in a cpu.

[Altera_Forum]

Hi Everyone,  

I'm using ALTERA DE1 Board series of EP2C20f484C7N . in this board how to define RAM Memory Blocks using QUARTUS II (version9.0).... following program is what I've written , please help me about any correction    library ieee; use ieee.std_logic_1164.all; entity simple_dual_port_ram_single_clock is generic  ( DATA_WIDTH : natural := 8; ADDR_WIDTH : natural := 6 ); port  ( clk : in std_logic; raddr : in natural range 0 to 2**ADDR_WIDTH - 1; waddr : in natural range 0 to 2**ADDR_WIDTH - 1; data : in std_logic_vector((DATA_WIDTH-1) downto 0); we : in std_logic := '1'; q : out std_logic_vector((DATA_WIDTH -1) downto 0) ); end simple_dual_port_ram_single_clock; architecture rtl of simple_dual_port_ram_single_clock is -- Build a 2-D array type for the RAM subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0); type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t; -- Declare the RAM signal.  signal ram : memory_t; begin process(clk) begin if(rising_edge(clk)) then  if(we = '1') then ram(waddr) <= data; end if;  -- On a read during a write to the same address, the read will -- return the OLD data at the address q <= ram(raddr); end if; end process; end rtl;