verilog code help!!

[Altera_Forum]

configuration cfg_sine_wave_tb of sine_wave_tb is 

for bench  for uut: sine_wave  use entity work.sine_wave(arch1);  end for;  end for; end cfg_sine_wave_tb;  this code is a test bench for a sine wave generator....but i dont understand exactly how this test bench works.....sine_wave_tb is as follows:  library IEEE; use IEEE.Std_logic_1164.all; use IEEE.Numeric_Std.all; use work.sine_package.all;  entity sine_wave_tb is end;  architecture bench of sine_wave_tb is  component sine_wave  port( clock, reset, enable: in std_logic;  wave_out: out sine_vector_type); end component;   signal clock, reset, enable: std_logic;  signal wave_out: sine_vector_type;   constant clock_period: time := 10 ns;  signal stop_the_clock: boolean;  begin   uut: sine_wave port map ( clock, reset, enable, wave_out );   stimulus: process  begin    -- Put initialisation code here   enable <= '0';  reset <= '1';  wait for 5 ns;  reset <= '0';   wait for 5115 ns;  enable <= '1';   -- Put test bench stimulus code here  wait for 1 ms;   stop_the_clock <= true;  wait;  end process;   clocking: process  begin  while not stop_the_clock loop  clock <= '1', '0' after clock_period / 2;  wait for clock_period;  end loop;  wait;  end process;  end;   to be specific...i wanna knw....wat does "for utt:sine_wave" mean...??!!

[Altera_Forum]

This isn't Verilog, it's VHDL. 

In VHDL you can define several architectures for the same block, for example a RTL architecture for synthesis and a functional one for test benches. The VHDL configuration block is used to tell the simulator what architecture to use. You can find more information about VHDL configurations here (http://www.doulos.com/knowhow/vhdl_designers_guide/configurations_part_1/)