verilog help case and for loop

Altera_Forum · ‎09-13-2012

Hi guys!, Can I simplify the followingin Verilog?:

always@(k)

case(k)

0: send_char = node[7+8*0:8*0];

1: send_char = node[7+8*1:8*1];

2: send_char = node[7+8*2:8*2];

3: send_char = node[7+8*3:8*3];

4: send_char = node[7+8*4:8*4];

5: send_char = node[7+8*5:8*5];

6: send_char = node[7+8*6:8*6];

7: send_char = node[7+8*7:8*7];

8: send_char = node[7+8*8:8*8];

9: send_char = node[7+8*9:8*9];

endcase

I thought of something like:

always@(k)

for(i=0; i<10; i=i+1)

if(i==k)

send_char = node[7+8*i:8*i];

But this does not work, because "k is not a parameter".

Thanks for your help! David

Altera_Forum · ‎09-13-2012

Try this:

assign send_char = node[(k*8) +: 8];

Altera_Forum · ‎09-13-2012

Thanks, that did the trick!

The assignment "node[start +: width]" specifies start and width of the sub-vector.

always@(k)

for(i=0; i<10; i=i+1)

if(i==k)

send_char = node[(i*8) +: 8];

Altera_Forum · ‎09-13-2012

Curious to know the need for that extra for loop. If you use signal k itself as the start index, you can code:

always@(k)

send_char = node[{k,3'b0} +: 8];

Altera_Forum · ‎09-13-2012

Thanks, that also works and is only two lines!