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Altera_Forum
Honored Contributor I
1,013 Views

very slow simulation of Arria 10 LVDS SERDES

Hi, 

 

has someone experience with simulating Arria 10 LVDS SERDES? I have to switch from Stratix iv to Arria 10 and I changed also the simulation models for the LVDS receiver. 

Simulation time has increased by a factor of 12! That's not usable (I need 8 hours to simulate 1 ms), so I used the Stratix iv SERDES models. 

Does someone have a better idea? 

 

Jens
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2 Replies
Altera_Forum
Honored Contributor I
66 Views

Is there any reason why you need to simulate them at all? if you are trying to validate your user logic, why not just generate data at the user logic input?

Altera_Forum
Honored Contributor I
66 Views

I need to simulate the Initialization and Reset for DPA. Furthermore I test the training sequence (bitslip) for the data interface.  

If this running right than I can switch to an internal (user logic) data generator. 

Why the simulation is slowed down so much for Arria 10 family? 

 

Jens
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