hello..juz wanna confirm.this is my question..
--Develop a VHDL model for an accumulator that calculates the sum of a sequence of fixed-point numbers. Each input number is signed with 4 pre-binary-point and 12 post-binary-point bits. The accumulated sum has 8 pre-binary-point and 12 post-binary-point bits. A new number arrives at the input during a clock cycle when the data_en control input is 1. The accumulated sum is cleared to 0 when the reset control input is 1. Both control inputs are synchronous.
and this is my code...
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is
port (clk,reset, data_en : in std_logic;
data_in : in signed(15 downto 0); --input declaration
data_out : out signed(19 downto 0) ); --output declaration
end entity accumulator;
architecture rtl of accumulator is
signal sum, new_sum :signed(19 downto 0);
begin
new_sum <= data_in + resize(data_in, 20); --operation of adder in accumulator
reg:process (clk) is
begin
if rising_edge(clk) then
if reset = '1' then
sum <= (others => '0');
elsif data_en = '1' then
sum <= new_sum;
end if;
end if;
end process reg;
data_out <= sum; --final output
end architecture rtl; --is it correct and suitable??plis do reply me asap..
--if there's sumthng wrong sumwhere,plis help me to correct it,,tq
