what is the difference between the sampling and clock frequency about FIR filter

[Altera_Forum]

hi,everyone.i want to ask whether the frequency of sampling and clock need to keep the same in use of fir compiler. according to my understanding,if they don't keep the same,the processing data rate can't keep consistent with the transmission rate which will lead the data loss or redundance. who can tell me that is it necessary that the sampling frequency should be equal to the data transmission rate and what is the difference of sampling frequency between AD and FIR filter.i mean ,after sampled by AD ,data go into the FIR filter .in that case ,how should i set the sampling frequency and clock.

[Altera_Forum]

The sampling frequency can be a fraction of the clock frequency, allowing for resource saving serial data processing.

[Altera_Forum]

Thank for your replying,but i still feel confused.For a FIR filter with fully parallel and certain sampling frequency, different clock frequency have different results(filtering effection), don't it?

[Altera_Forum]

--- Quote Start ---  Thank for your replying,but i still feel confused.For a FIR filter with fully parallel and certain sampling frequency, different clock frequency have different results(filtering effection), don't it?  --- Quote End ---    true of course and you the designer must make sure you clock the stream at the correct sampling rate. The easiest way is to have a clock same as sampling rate.

[Altera_Forum]

--- Quote Start ---  true of course and you the designer must make sure you clock the stream at the correct sampling rate. The easiest way is to have a clock same as sampling rate.  --- Quote End ---    Thank YOU.when we use fir compiler,we need set the value of Fs.so, i want to know that is it necessary that Fs must be equal to the front AD's sampling frequency.the Fs decides what performances about FIR .besides, is it have effect on data transmission? for example, the AD's sampling frequency is 100MHZ,signal's bandwidth is 40MHZ,which value i need choose for the Fs and clock frequency about FIR filter.

[Altera_Forum]

The input sampling rate of the FIR is the word rate of the data stream and will be equal to the ADC rate unless you have decimation stages inbetween. The actual sampling frequency is commanded by the asynchronous stream handshake, the sampling frequency number used in filter design is a nominal value for calculation. 

 The FIR clock frequency must be equal or greater compared to the sampling frequency, otherwise a data overflow occurs.  P.S.: As a simple case, use Fs = Fclk and set the input handshake signal to '1'.

[Altera_Forum]

--- Quote Start ---  Thank YOU.when we use fir compiler,we need set the value of Fs.so, i want to know that is it necessary that Fs must be equal to the front AD's sampling frequency.the Fs decides what performances about FIR .besides, is it have effect on data transmission? for example, the AD's sampling frequency is 100MHZ,signal's bandwidth is 40MHZ,which value i need choose for the Fs and clock frequency about FIR filter.  --- Quote End ---    If your adc is sampling the signal at 100 Msps then this is Fs of your stream.  The clock can be 100MHz or multiple. I will assume you already have the ADC clock of 100MHz so just use it in FPGA