whether there is some component like IOdelay in Xilinx FPGA?

[Altera_Forum]

Whether there is some component in altera FPGA like IOdelay in Xilinx FPGA?

[Altera_Forum]

The altiobuf has a dynamic delay chain that can be configured(Stratix family). Most people do NOT use it like Xilinx. For Altera devices, if you put in timing constraints it will set the IO delay chain to the best value for margin across PVT. Also, you can force it with assignments in the Assignment Editor, such as D2 Delay Chain... (There are multiple delay chains for some of the I/O, so be sure to look in the handbook). But probably 95% of users just do I/O assignments, 4% force the delay chain to values in the Assignment Editor, and less than 1% dynamically modify it. What is it you're trying to do?

[Altera_Forum]

--- Quote Start ---  The altiobuf has a dynamic delay chain that can be configured(Stratix family). Most people do NOT use it like Xilinx. For Altera devices, if you put in timing constraints it will set the IO delay chain to the best value for margin across PVT. Also, you can force it with assignments in the Assignment Editor, such as D2 Delay Chain... (There are multiple delay chains for some of the I/O, so be sure to look in the handbook). But probably 95% of users just do I/O assignments, 4% force the delay chain to values in the Assignment Editor, and less than 1% dynamically modify it. What is it you're trying to do?  --- Quote End ---     I do design with 384mbps serdes interface.(look the attachment) And I had used the IP core below.   altlvds_rx_component : altlvds_rx  GENERIC MAP (  common_rx_tx_pll => "ON",  deserialization_factor => 12,  implement_in_les => "ON",  inclock_data_alignment => "UNUSED",  inclock_period => 31250,  inclock_phase_shift => 0,  input_data_rate => 384,  intended_device_family => "Cyclone IV E",  lpm_hint => "CBX_MODULE_PREFIX=lvds_rx",  lpm_type => "altlvds_rx",  number_of_channels => 8,  pll_self_reset_on_loss_lock => "OFF",  port_rx_channel_data_align => "PORT_USED",  registered_data_align_input => "OFF",  registered_output => "ON",  use_external_pll => "OFF"  )  PORT MAP (  pll_areset => pll_areset,  rx_inclock => rx_inclock,  rx_cda_reset => rx_cda_reset,  rx_in => rx_in,  rx_channel_data_align => rx_channel_data_align,  rx_locked => sub_wire0,  rx_out => sub_wire1,  rx_outclock => sub_wire2  );   the Fck is used as rx_inclock. At this case,is there need to add timing constraints?

[Altera_Forum]

I think you do, but can't remember. The Stratix family has dedicated serializers and the timing report is automatic by running Report RSKM in TimeQuest. If that doesn't return anything, than you will want timing constraints. Note that the data and clock are coming in edge-aligned, so the FPGA needs to center-align the clock. The external clock is just a virtual clock, just at the 192MHz period. Then just do two sets of set_input_delay to say it is sending data on both the rising and falling edge: 

set_input_delay -clock virt_192 -max 0.0 [get_ports {din[*]}] set_input_delay -clock virt_192 -min 0.0 [get_ports {din[*]}] set_input_delay -clock virt_192 -max 0.0 [get_ports {din[*]}] -clock_fall set_input_delay -clock virt_192 -min 0.0 [get_ports {din[*]}] -clock_fall Change the -max and -min values to show how much skew there is on the data. Note that your setup relationship should be half_data_window and hold relationship should be -(half_data_period). (This is all if report_rskm doesn't return anything, which I don't think it will)