why the waitrequest signal is always 0

[Altera_Forum]

hi,all.I wanna use an arbitrator for two frame buffer to access the DDR3 SDRAM (IP:DDR3 SDRAM Controller with UniPHY Device:cyclone V Tool:QuartusII 13.0).But I find the read_waitrequest and write_waitrequest of the MPFE are always '0',is that wrong?When I derect connct the frame buffer to the MPFE,the signal of these two waitrequest all be ‘1’. 

And in the Avalon Interface Specification:  "A master must make no assumption about the assertion state of waitrequest when the master is idle: waitrequest may be high or low,depending on system properties." "an avalon-mm slave may assert waitrequest during idle cycles.an avalon-mm master may initiate a transaction when waitrequest is asserted and wait for that signal to be deasserted. to avoid system lockup, a slave device should assert waitrequest when in reset" Why my waitrequest signal is always ‘0’?Dose the MPFE must be initiazation?

[Altera_Forum]

Hello, I am also struggling with the DDR3 UniPhy, I do have better luck that my waitrequest is deasserted most of the time except when I am hit with efficiency issue. From my debug, you should not pull read/write request until the waitrequest is cleared, this is especially true when local_init_done is just asserted, and/or after performed manual refresh. Hope this helps.

[Altera_Forum]

hi,jenglee,thank you for your reply.My local_init_done is asserted but the waitrequest signal never deasserted,so I don't know how to do next step.And I haven't do any request after reset.

[Altera_Forum]

Actually I don't recommend that. Masters should issue read or write transactions regardless of the state of the waitrequest signal. From the master perspective, waitrequest just informs the master that the read/write transaction must be prolonged. The Qsys fabric has an undefined waitrequest behavior when the master is not issuing a read or write transaction so if your master is waiting for waitrequest to be low before issuing a transaction you might deadlock that master since it could wait indefentely. 

 The memory controller uses an active low waitrequest because it uses it's internal ready signal (so when it's not ready waitrequest should be issued back to the fabric). So when the slave port is ready to handle data you should see the SDRAM slave port waitrequest_n (should be called avl_ready_x, where x is the port number) set to 1. If you see it set to 0 that means either it has buffered up so many transactions that it needs to backpressure or it's command FIFO is full and it's still calibrating.

[Altera_Forum]

My signal is waitrequest(not waitrequest_n),and it may asserted by '1',and I think it would be set to '0' when the slave at the state of IDLE,right?

[Altera_Forum]

Not necessarily. When your master isn't issuing a read or write transaction, it might see waitrequest driven high. A properly design master should ignore waitrequest if it is not reading or writing

[Altera_Forum]

it seems the waitrequest dosen't go high at idle time,I cann't exactly reading or writing.