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x2 PCIE Design

Altera_Forum
Honored Contributor II
‎06-05-2013 04:02 AM
1,503 Views

Hi, 

 

I would like to design a x2 PCIE Gen 2.0 root port. In the system settings in Avalon MM Hard IP for PCIE, the option for number of lane is only x1 and x4. It says that if I will design x2 lane, I will select the x4 and do downtraning. 

What is meant by downtraining? 

 

 

Thanks 

 

Regdrs
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Altera_Forum
Honored Contributor II
‎06-05-2013 05:41 AM
688 Views

Apparently, the term refers to PCIe link width determination during link training 

 

PCIe spec says 

 

--- Quote Start ---  

The following are discovered and determined during the training process: 

�� Link width 

�� Link data rate 

�� Lane reversal 

�� polarity inversion 

--- Quote End ---  

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Altera_Forum
Honored Contributor II
‎06-06-2013 02:25 AM
688 Views

Sorry, I did not understand. What is Link training? When does it happens?

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Altera_Forum
Honored Contributor II
‎06-15-2013 12:57 AM
688 Views

I'm wondering if study LTSSM operation can make you understand more?

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