for 4096 TLP packet size there are four clock shifts that can occur for gen1 speed and X1 pipe width( four clock cycles difference between recovered clock and local clock).
but the description in the below document is saying the following. (the PHY can add or remove one SKP symbol (PCIe* Mode at 2.5 or 5 GT/s),
PHY Interface for the PCI Express*, SATA, USB 3.2, DisplayPort*, and USB4 Architectures
August 2021 Revision 6.1
For the Nominal Half Full buffer model, the PHY is responsible for inserting or removing
SKP symbols, ordered sets, or ALIGNs in the received data stream to avoid elastic
buffer overflow or underflow. The PHY monitors the receive data stream, and when a
Skip ordered set or ALIGN is received, the PHY can add or remove one SKP symbol
(PCIe* Mode at 2.5 or 5 GT/s), four SKP symbols (PCIe* Mode at 8 GT/s, 16 GT/s, or
32 GT/s), one SKP ordered set (USB Mode at 5 GT/s), or one ALIGN from each SKP or
ALIGN as appropriate to manage its elastic buffer to keep the buffer as close to half full
as possible
could you please clarify what could be the reason for adding or removing only SKP symbol instead of four SKP symbols.
