We are writing a graphics driver for the Intel 855GME Chipset running under QNX. We are using the Intel 965 Express Chipset Family Programmers Reference Manual. Volume 3 Display Registers is an excellent reference for setting registers pertaining setting up the LVDS pipe and planes. We are using a scope to measure the frequencies of CLK, HSYNC and VSYNC signals once the DPLL, plane and pipe are enabled. For CLK we expect 65mHz at 1024x768 resolution but we observe 23 Mhz. For VSYNC we expect 60hz but we observe 18hz For HSYNC we expect 48 kHz but we observe 15 kHz. How can we control the DPLL and display clock to effect the proper signal frequencies.
