Its not entirely clear if this is a continuation of Labree where if I understood things correctly the individual processors on the die lacked inter-processor cache coherency (requiring external serialization when necissary), or if phi is some sort of evolution of existing multi-core architectures where inter-processor cache coherency is maintained.
I agree its an interesting processor from a virtualization standpoint either way, but its also not clear what instruction sets each core in a phi part supports, so what kind of virtualization software to make it interesting changes quite a bit depending on the answers to the cache coherency and instruction set question. The link Quoc-tahi Le posted didn't seem to contain any actual technical information.
