Assemblers for the new instructionset

[Paul_C_7]

Hi I am interested in porting our code generator generator to the Xeon Phi. In order to do that I need a formal machine description which I can fairly readily write - though the use of 1 bit masks in the vector mask registers may cause a bit of trouble - the bigger problem is to have a syntax for the assembler code. I know that there is as yet no nasm assembler. Is there a Gnu assembler, and if so does it use the Intel syntax or the old gnu syntax ?

[Kevin_D_Intel]

A GNU assembler ships/installs with MPSS. $ /usr/linux-k1om-4.7/bin/x86_64-k1om-linux-as --version GNU assembler (GNU Binutils) 2.22.52.20120302 Copyright 2012 Free Software Foundation, Inc. This program is free software; you may redistribute it under the terms of the GNU General Public License version 3 or later. This program has absolutely no warranty. This assembler was configured for a target of `x86_64-k1om-linux'. Refer to MPSS 2.1 "Gold" released for details on obtaining MPSS

[Paul_C_7]

where can I find a syntax spec for the gnu assembler for the new instructuons.

[Kevin_D_Intel]

ABI details and instruction set syntax are available under the sticky RESOURCES (including downloads) post. I'm not aware of others.

[Paul_C_7]

If you mean "Intel Xeon Phi Coprocessor Instruction Set Architecture Reference Manual", I downloaded that a while back. Is that the actual syntax used by the assembler that you release though, since the gnu syntax is usually rather different from the intel syntax?

[Kevin_D_Intel]

Yes, that is the reference I meant. I believe I have this correct. The assembler accepts GNU-style (i.e. AT&T* assembly syntax - destination operands appear on the right; source operands on the left) and the notation used in the instruction set manual (as described in section 3.6) mimics Intel syntax (operand order is the reverse of AT&T*).

[Paul_C_7]

Ok that is great we should be able to convert our AVX code generator to use the new syntax fairly trivially just by altering the definition of the vector lengths then since the 3 operand opcodes are the same. All I need now is somebody in the UK who will quote for Phi system.

[Kevin_D_Intel]

On the product brief here: https://www-ssl.intel.com/content/www/us/en/processors/xeon/xeon-phi-detail.html Scroll to the bottom to find the PDF: Where to Buy: Growing Intel® Xeon Phi™ Coprocessors Adoption (direct link is: https://www-ssl.intel.com/content/www/us/en/processors/xeon/xeon-phi-coprocessor-where-to-buy.html)