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Andrew_K_
Beginner
49 Views

Atomic access to two 32-bit MMIO registers

My apologies for posting in this section - I couldn't find a better fit.

I am trying to program SPI flash access tool supporting ICH10 chipsets. I'm utilizing a device integrated in PCH exposed on a PCIe bus. In order to issue a flash operation, one needs to write to two 32-bit MMIO registers of said device. One of the register contains the address of the operation and the second one the type of operation. I want to ensure this is handled atomically, i.e. both registers written at once without the possibility of other code (interrupts, SMM) trashing one register before I write the other.

Is compare-exchange instruction with 64-bit operands a valid way of achieving this? This register pair is 4-byte aligned (so it would be an unaligned access). I do not possess low-level PCIe knowledge and am wondering whether this atomicity needs to be supported by the root complex and/or the PCIe device.

For specific details, refer to "Intel® 100 Series Chipset Family Platform Controller Hub (PCH) Datasheet - Volume 2", page 476.
Registers BIOS_HSFSTS_CTL, BIOS_FADDR are what I'm after.

Regards,
Andrew

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2 Replies
Harold_G_Intel
Employee
49 Views

Hi,

For assistance on chipsets, you may want to post to our communities below:

https://communities.intel.com/community/tech/chipsets

Regards, Hal

Intel(R) Developer Zone Support

http://software.intel.com
*Other names and brands may be claimed as the property of other

SergeyKostrov
Valued Contributor II
49 Views

>>...I want to ensure this is handled atomically... - Use a critical section, or another synchronization object available in a language you're programming - Then boost priority of the current processing thread to real-time - Wait for a couple of clock cycles to ensure that all other threads are pre-empted - Then complete a procedure with registers
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