DVFS on Intel SandyBridge

[sbhal1]

Hi All,

I wanted to experiment with DVFS on Intel SandyBridge and through the Intel Manual 3B, I see that the DVFS is achieved on SandyBridge using Enhanced Intel SpeedStep.

It says that IA32_PERF_CTL could be set to achieve DVFS. However the Manual does not explain how to set the lower 16 bits in IA32_PERF_CTL to achieve this. I went across searching on different forums to ascertain how to set this to no avail. However, what I could learn is that the 16 bits are divided into two 8-bit blocks that specify the Multiplier and VID. 

I also found that the multiplier can be found on intel sandy bridge as

• [CPU frequency] = BCLK x [CPU multiplier].

I am using a Xeon E5-2680 with 2.7GHz. The data sheet says the BCLK0 and BCLK1 are 100MHz(Table:6-11).

So the current multiplier seems to be 27.

The VID range is 0.60V-1.35V.

1. Now if I have to scale the frequency, do the go about changing 8-MSB(15-8) to any value lesser than 27 only?

2. Or do I need to change the 8-LSB(7-0) between 0.6 and 1.35V.

I am aware that SandyBridge has a limited set of P-states from P0 to PN and I just can't go about setting the 16-bits as per my will.

So, What I basically wanna know is how do I do DVFS on SandyBridge?

PS: Please correct me if my understanding so far is incorrect.

Thanks in advance.

Best,

Sridutt

[Mohammad_Ashraful_An]

Hi sridutt,

Were you able to find the information? I am trying to do something similar in Haswell.

[sbhal1 · Accepted solution]

Hi,

I wasn't able to use IA32_PERF_CTL to do DVFS. However, I used the cpufreq module that exposed the various available frequencies to choose from. By changing the scaling governor to "userspace", you can set any of the available frequencies in the "setspeed" to run at the desired frequency.

A comprehensive post explaining how this can be done is "Enhanced Intel SpeedStep® Technology and Demand-Based Switching on Linux" ​that can be found here. The explanation for setting up CPUfreq on unix can be found here.

And the above approach is supported on Haswell too. Frankly, it has gone better as you can set different frequency on each core, unlike the same frequency that was required on Sandybridge.

Hope this helps.

Best,

Sridutt