Dynamic voltage/frequency scaling

[solange1234]

Intel has several processors that support dynamic scaling of voltage and frequency. However, it is almost impossible to find the information regarding frequency ranges on different processors. Intel's processorfinder website and even Intel's pages dedicated to specific processors do not have this information. Any idea where I could find this?

(If this is not the right forum for this question, could you recommend where I should post?)

[_void_]

I was trying to get speedstep information on a specific C2D processor and the reply was that this information is not public and is only available to BIOS writers. What you can do however (if you have the processor available) is use programs such as CPUZ (CPUID) to get frequency, bus, core voltage, etc. and then play with the multipliers and the core voltage settings. The core voltage settings are trickier because they depend on the hardware board support your processor has. If you are using linux try to use the resources available through the ACPI.

[solange1234]

Thanks. This would be a non-problem if I had the processor available. But I need to decide on the kind of machine to buy - that's why I need to know the supported frequency ranges!

[_void_]

To figure out the frequency range you should be able to find the maximum rated frequency and the bus speed of the processor and then use those to figure out what the maximum multiplier is, and I've been told that the minimum multiplier you can use is 6X. For example on the E6750 the max frequency is 2666 MHz and the nominal bus speed is 333 MHz so the *stock* multiplier is 8X. 6X will take it down to 2000 MHz. I can'ttell you how to match the core voltage though cause thats hardware dependent (and not publicly documented).

[Intel_Software_Netw1]

Our engineering contacts responded:

This question is basically asking what the possible P-states are for a processor. P-states are a combination of core clock frequency multiplier (ratio) and voltage (VID) for a specific ratio.

The ratio and VID information is not in public documentation. The VID for a given processor ratio is based on a calculation published in the Bios Writers' Guide and can impact processor operation if the wrong VID is specified for a given ratio.

FYI: How to extract the information depends on the type of processor (Pentium 4, Core2, etc.). The Intel 64 and IA-32 Architectures Software Developer's Manual does not discuss the specific register bits for extracting the ratio range and VID range. Not discussing the ratio min and ratio max bits as well as not discussing the VID min and VID max bits is likely intentional, so that rogue software isn't easy to write.

We only discuss the ratio and VID range bits within the processor specific BIOS Writer's Guide (BWG). The ratio and VID register locations and bit field widths are intentionally not defined as architectural -- by this we mean they are intentionally allowed to reside anywhere within a processor model MSR space. Being non-architectural is OK, because the BIOS is platform-specific and will have prior knowledge about which processor models the platform supports, and thus the model specific location of the ratio and VID information.

The processor's reported range for the ratio and VID is not an accurate way to determine the valid P-states. For example, when your laptop is in battery mode, the processor does not change the ratio and VID range information. Instead, the BIOS and OS cooperate: there is an ACPI mechanism where the BIOS can limit the available P-states without having to modify the ACPI P-state tables.

Assume a processor has 6 p-states where P-0 is the highest performance/power (high ratio & high VID) state and P-5 is the lowest performance/power (low ratio & low VID) state. Given the above battery example, the BIOS may tell the OS that the valid range of P-states is P-3 through P-5, while on AC the valid P-states might be reported as P-0 through P-5. Notice the lower limit never changes, but the upper limit (lower P-state # = higher perf / higher power) does, based on platform parameters like AC vs. Battery. Thermals can also impact the P-state upper limit reported to the OS. Intel Dynamic Acceleration Technology (IDA, i.e., Turbo mode) also adds another level of complexity the BIOS understands, but the OS is ignorant of, and turbo is not available as a ratio / vid tuple reported by the processor. One last complexity related to ratio and vid is Bus Geyserville, which is the ability to throttle the front side bus speed. Again, Bus Geyserville is not a capability that is reported by the ratio and vid tuples of the processor, yet it is exposed by BIOS as the lowest P-state.

To summarize, P-state table construction requires explicit knowledge by the BIOS of features such as IDA and Bus Geyserville, in addition to knowing where for a specific processor model to extract the max ratio, max VID tuple and min ratio, min VID tuple.

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Lexi S.

IntelSoftware NetworkSupport

http://www.intel.com/software

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