I have not looked at all of the different models, but the Xeon Phi SE10P with ECC enabled uses a block-oriented memory mapping.
Starting at the beginning of the physical address space (address 0), consecutive 62-cache-line blocks of physical addresses are assigned to channel 0 on one of (a permutation of) the 8 memory controllers. Subsequent 62-cache-line blocks are assigned to channel 1 on the same permutation of the 8 memory controllers. For subsequent 62-cache-line blocks the mapping is repeated until the top of memory is reached.
Because the blocks are 62 cache lines in size, each 4KiB virtual memory page has its cache lines split between exactly two DRAM channels (one on each of two different memory controllers). Up to 62 of the 64 cache lines of a 4KiB page can be mapped to a single DRAM channel, with all even-numbered splits occurring (2+62, 4+60, 6+58, etc) at various addresses.
Because each 4KiB page is guaranteed to only access 2 DRAM channels, it is theoretically possible to set up an application to use only a subset of the 8 memory controllers and 16 DRAM channels. It would not be very much fun, but it is theoretically possible.
