We are trying to make a peer-to- peer transaction between 2 End-Points, through Intel chipset without succession. (Not through CPU/ CPU memory).
The 2 E.P. connected to PCIe channels of the QM57 \ QM77 \ QM170.
There is communication between the EP and the CPU/CPU memory. but not peer-to- peer between the 2 E.P.
Does the QM57 \ QM77 \ QM170 support PCIe peer-to- peer?
How should we config the QM57 \ QM77 \ QM170 so it would support peer-to-peer cycles.?
We are using OS windows CE6.
We familiar with accessing registers directly with configuration, memory and I/O transactions.
