Questions about memory cache control

changhee · ‎01-07-2005

First of all, thanks for your reading.

I havetwo questions about memory cache control.

"1. Do store buffers operate when disabling caches?"

"2.Ifsome memory regions are set to WC(write combining), dothe readsto the regionsrefer to write combining buffers, not to memory? If the reads refer to write combining buffers, is it possible toflush the buffer explicitly?"

If you have any idea, please let me know.

I look forward to replying.

Message Edited by changhee on 01-07-2005 10:12 AM

Message Edited by changhee on 01-07-2005 10:16 AM

Intel_Software_Netw1 · ‎01-26-2005

We are forwarding your question to our engineering contacts and will let you know how they respond.

Adetailed discussion of memory cache control can also be found in Chapter 10 of the IA-32 Intel Architecture Software Developer's Manual, Volume 3: System Programming Guide (http://developer.intel.com/design/pentium4/manuals/index_new.htm#sdm_vol3).

Regards,

Lexi S.

IntelSoftware NetworkSupport

http://www.intel.com/software

Contact us

Message Edited by intel.software.network.support on 12-02-2005 08:41 PM

Intel_Software_Netw1 · ‎02-07-2005

Here is the response we received from our engineering contacts:

Q1. Do store buffers operate when disabling caches?

A1. Yes. Store buffers operate regardless of the memory type of the target address or whether cache is disabled or not.

Q2. If some memory regions are set to WC (write combining), do the reads to the regions refer to write combining buffers, not to memory? If the reads refer to write combining buffers, is it possible to flush the buffer explicitly?

A2. Yes. If the write combine buffer is not flushed, the data will come from the WC buffer. Cache Line Flush instruction (clflush) will flush the cache line containing the specified address from all levels.