Replace default serial console/debug port with high speed UART1/2

[JBize]

I have a MinnowBoard Turbot.  I'd like to create a UEFI image that uses the (first) high speed UART port as the serial console and optionally the debug port.

Is that possible?  If so, how?

[JBize]

Ideally, I would only have to drag the "UART Header" onto "HSUART0" on the diagram.  But that doesn't work. 

[Jarlstrom_Intel]

Yes it is possible.

You need to set the following PCDs:

 you need to set PcdLpssPciModeEnabled to "PCI" mode.
gEfiVLVTokenSpaceGuid.PcdLpssPciModeEnabled | 0x01

  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate              |115200
  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE
  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio               |TRUE
  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase          |0xF0000000
  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl           |0x03
  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl           |0x07
  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable           |FALSE
  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride        |4
  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate             |44236800
  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialPciDeviceInfo         | {0x1E, 0x03, 0x84, 0x00, 0xFF}

Optionally if you are using the Intel Firmware Engine

Under Settings -> Common Settings Set the following:

LPSS & SCC Devices Mode:  PCI Mode
Baud rate for serial port: 115200
Serial Port Clock Rate: 44236800

uncheck Enable serial port cable detection

Serial Port FIFO Control settings:
 Check FIFO enable
 Check Clear receive FIFO
 Check Clear transmit FIFO
 uncheck Enable 64-byte FIFO

Serial port Line Control settings:
 Data bits: 8 bits
 Stop bits: 1 bit
 Parity:  No Parity

PCI Serial Device Info: 0x1e, 0x03, 0x84, 0x00, 0xff

Base address of serial port registers: 0xF0000000

Serial Port Register Stride in Bytes: 4

 uncheck Enable serial port hardware flow control
 
 check Serial port register use MMIO

[JBize]

Thanks.  I tried the Intel Firmware Engine settings.  (I had a few parameters that were different.)  Unfortunately, although I now get the log output on HSUART0, I doesn't start a UEFI shell.  It just hangs.

[JBize]

Update: 

I am unable to get the Intel Firmware Engine to put the "UART Console" onto the correct UART (HSUART0). 

I can do it in the diagram, however it doesn't change the Console port (stays at UART).  If I set the "Serial Port Clock Rate" to 44236800, I get the console logging output on the desired port (HSUART0), but I get no UEFI Shell.  If I set the "Serial Port Clock Rate" to 1843200, I get no logging output, but I get the UEFI Shell on the original wrong port (UART).

So the "Serial Port Clock Rate" appears to be used by both the console and the debug logging, and I am unable to actually use HSUART0 for the console.

Update 2:

When I attempt to build in Windows from the EDK2 sources, it fails with the following:

    build...
    c:\myworkspace\edk2-platforms\Vlv2TbltDevicePkg\PlatformPkgIA32.dsc(952): error F001: Pcd (gEfiVLVTokenSpaceGuid.PcdLpssPciModeEnabled) defined in DSC is not declared in DEC files. Arch: ['IA32']

It seems I have no references to any "PcdLpss..." PCDs in my source tree; What am I missing?

[JBize]

Can I get more help on this please?

[Jarlstrom_Intel]

It seems that the PCD PcdLpssPciModeEnabled is not part of the Minnowboard Max/Turbot source code from https://firmware.intel.com/projects/minnowboard-max but is part of the Intel Firmware Engine as part of the Settings -> Common Settings. 

However, there is a setup switch if you go into setup by selecting "Device Manager" - > "system Setup" -> "South Cluster Configuration" -> "LPSS & SCC configuration" then select LPSS & SCC Devices " to "PCI Mode"

[JBize]

Thanks for the update.  I was trying different combinations of edk2 git versions to find one with that PCB.  Anyway, my SF-100 is currently visiting another state for a while, so I don't know when I'll be able to get back to this.  I can use the UEFI shell to do updates, but once I brick it, I'll have to wait for the SF-100 to return.

However, I may have found an issue with the Firmware Engine.  Changes I made to the diagram didn't seem to do anything, but once I expanded and changed (unrelated) settings on diagram components, the diagram changes took effect.  So now, I have BOTH the UEFI console and debug appearing on the first HSUART.  

There are lots of "bad" characters on the display, and it asks for a BREAK character, but it's mostly working now... I think.

[JBize]

I'd like to refresh this thread and hopefully get some help.  I can get the debug log output onto HSUART1, but now I need to boot the UEFI shell, menu, and Linux to that port.

i.e.: I need an "IA32 Release UEFI" image that uses HSUART1 (ttyS1) instead of the default UART (ttyS0).

I am unable to do that with either the Firmware Engine, or the edk II source code.

Can anyone help?  I've spent hours (days) on this.

Can it even be done?