This is what I found in the Intel Xeon Phi coprocessor Instruction Set Architecture reference:
Writes to overlapping destination memory locations are guaranteed to be ordered with respect to each other (from LSB to MSB of the source registers). Only writes to overlapping vector indices are guaranteed to be ordered with respect to each other (from LSB to MSB of the source registers). Writes that are not overlapped may happen in any order. Memory ordering with other instructions follows the Intel-64 memory ordering model. Note that this does not account for non-overlapping indices that map into the same physical address locations
From this, I deduce that same indices are allowed in a scatter instruction. Also, since the overlapping writes are ordered from LSB to MSB of the souce elements, I would expect the MSB value to be actually present in the memory location after the scatter has been executed.
