mux1 vs mux2 on IA-64

[Adam]

Why is it that mux1 only has five possible permutations, whereas mux2 has any possible permutation?

I was searching "the entire Internet" for the answer, and I couldn't find it. Maybe an Intel Itanium engineer can brief me on this one?

Thanks,

Adam

[Terence_S_Intel]

Quoting - Adam Kachwalla

Why is it that mux1 only has five possible permutations, whereas mux2 has any possible permutation?

I was searching "the entire Internet" for the answer, and I couldn't find it. Maybe an Intel Itanium engineer can brief me on this one?

Thanks,

Adam

mux2 operates on 4 elements. Therefore, you need 8-bitsin the instruction decode field (4 elems x4 possible destinations = 4 x 2 bits) to have all possible permutations.

mux1 operates on 8 elements. To have all possible permutations, you would need 24-bits in the instruction decode field (8 elems x8 possible destinations = 8 x 3 bits). Because only 8-bits are available in the instruction coding, a set of 5 common permutations are provided.

[Adam]

Quoting - Terence Sych (Intel)

Quoting - Adam Kachwalla

Why is it that mux1 only has five possible permutations, whereas mux2 has any possible permutation?

I was searching "the entire Internet" for the answer, and I couldn't find it. Maybe an Intel Itanium engineer can brief me on this one?

Thanks,

Adam

mux2 operates on 4 elements. Therefore, you need 8-bitsin the instruction decode field (4 elems x4 possible destinations = 4 x 2 bits) to have all possible permutations.

mux1 operates on 8 elements. To have all possible permutations, you would need 24-bits in the instruction decode field (8 elems x8 possible destinations = 8 x 3 bits). Because only 8-bits are available in the instruction coding, a set of 5 common permutations are provided.

Couldn't you use an imm₂₄ field?

[Terence_S_Intel]

Quoting - Adam Kachwalla

Couldn't you use an imm₂₄ field?

There isn't enough space in a 41-bit instruction for a 24-bit field.

For mux1/mux2, you need 6-bits for QP, 14-bits for r1 and r2, 13-bits for opcode and extensions. That leaves the 8-bits for the permutations.

[Adam]

Quoting - Terence Sych (Intel)

There isn't enough space in a 41-bit instruction for a 24-bit field.

For mux1/mux2, you need 6-bits for QP, 14-bits for r1 and r2, 13-bits for opcode and extensions. That leaves the 8-bits for the permutations.

So then how do some instructions (such as movl) take imm₆₄ fields?

[Terence_S_Intel]

Quoting - Adam Kachwalla

So then how do some instructions (such as movl) take imm₆₄ fields?

Those instructions are special cases where you need to encode an address in the instruction. For the sake of simplicity, you'd like to severely limit those uses.

[Adam]

Quoting - Terence Sych (Intel)

Those instructions are special cases where you need to encode an address in the instruction. For the sake of simplicity, you'd like to severely limit those uses.

What about:

(qp)movl r₃=imm₆₄

(qp)mux1 r₁=r₂, r₃

Or is mux1 like how it is so that only one instruction is needed?

[Terence_S_Intel]

Quoting - Adam Kachwalla

What about:

(qp)movl r₃=imm₆₄

(qp)mux1 r₁=r₂, r₃

Or is mux1 like how it is so that only one instruction is needed?

movl needs to have an imm64 field. mux1 doesn't really need to. If mux1 did, it would make instruction decode much more difficult.