some figures in "Intel® Xeon PhiTM Coprocessor System Software Developers Guide" are in very low quality

siyao_z_ · ‎04-05-2013

As the title said, for example section "2.1.12 Host and Intel® MIC Architecture Physical Memory Map", the figure is unrecognizable, and the list below the figure is also fault in hierarchy. By the way, the overall quality of this document is not as good as Intel's 3-set software development manual. Do you have plans to fix this document? Thanks!

robert-reed · ‎04-07-2013

While I would not agree that the figure is unrecognizable, it does appear that resolution limits in the production of the PDF have resulted in degradation of some of the addresses and block labels to the point of illegibility. The diagram needs to be larger to improve the readability of the document. I will ask about that. However, I do not see any errors in the content.

Information about the Intel Xeon Phi coprocessor has not yet been integrated in the magnum opus, the Software Developers Manual. Though I have not heard of any plans or schedules for incorporating the appropriate parts of this Intel Xeon Phi coprocessor system programmer's guide into that larger document, it seems reasonable to expect that those details will be incorporated sometime in the future. If you have more specific claims about the quality of this system developers guide, please share them and we will try to get them fixed.

siyao_z_ · ‎04-07-2013

robert-reed (Intel) wrote:

While I would not agree that the figure is unrecognizable, it does appear that resolution limits in the production of the PDF have resulted in degradation of some of the addresses and block labels to the point of illegibility. The diagram needs to be larger to improve the readability of the document. I will ask about that. However, I do not see any errors in the content.

Information about the Intel Xeon Phi coprocessor has not yet been integrated in the magnum opus, the Software Developers Manual. Though I have not heard of any plans or schedules for incorporating the appropriate parts of this Intel Xeon Phi coprocessor system programmer's guide into that larger document, it seems reasonable to expect that those details will be incorporated sometime in the future. If you have more specific claims about the quality of this system developers guide, please share them and we will try to get them fixed.

Thanks for you reply!

This document is very informative, helps us a lot on understanding the architecture of Intel MIC. As far as I can figure out, I found following tiny flaws in this doc:

* figure 2-3 on page 18: illegible figure

* figure 2-12 on page 34: illegible figure. I thinks it would be much better if all the figures in this doc are supplied in vectorized format, most of which are, but a few of which are not.

* the list below "The Local Address Range 0x00_0000_0000 to 0x0F_FFFF_FFFF (64 GiB) is further divided into 4 equal size ranges: " on page 34 should be:

0x00_0000_0000 to 0x03_FFFF_FFFF (16 GiB)
GDDR (Low) Memory
Local APIC Range (relocatable) 0x00_FEE0_0000 to 0x00_FEE0_0FFF (4 kB)
Boot Code (Flash) and Fuse (via SBOX) 0x00_FF00_0000 to 0x00_FFFF_FFFF (16 MB)
0x04_0000_0000 to 0x07_FFFF_FFFF (16 GB)
GDDR Memory (up to PHY_GDDR_TOP)
0x08_0000_0000 to 0x0B_FFFF_FFFF (16 GB)
Memory mapped registers
DBOX registers 0x08_007C_0000 to 0x08_007C_FFFF (64 kB)
SBOX registers 0x08_007D_0000 to 0x08_007D_FFFF (64 kB)
Reserved 0x0C_0000_0000 to 0x0F_FFFF_FFFF (16 GB)

* figure 2-13 on page 37: illegible figure

* figure on page 38 is a duplication of figure 2-14 on page 39. this figure shouldn't be here I guess..

robert-reed · ‎04-07-2013

And thanks for sharing the additional details. I'll be sure to alert the author regarding your comments so something can be done about them.