I recently managed to get my fingers on an x200 Knights Landing coprocessor card and it's so much fun to play with.
I want to do some hobby osdev on it, so I'm looking for debug interfaces other than shared memory and I have a few questions. Maybe somebody knows more about the card than what is documented publicly:
Come on, Intel! The card is EOL anyway, please give us nerds a bit more information to play with!
edit: Okay, the USB port IS an EHCI debug port. Nice! Thanks for putting that on the card even though it's not documented anywhere.
After I set up a beaglebone and loaded the right USB EHCI debug gadget module, I am getting UEFI boot debug output and the early kernel log. Pretty dope.
The UEFI boot however seems to be very verbose. It resets multiple times (no idea if that's normal?) and then gets further and further in booting until it spits a whole bunch of register contents over the debug port. That would explain why it takes so long for the card to boot. I also don't see where exactly it loads the OS. The output seems to be only from the PEI phase. I might be wrong though.
edit2: I did some more digging. After I found the "S7200AP System Integration and Service Guide" which is a blade with a Xeon Phi Knights Landing CPU, I saw the same 60 pin Samtec connector. It is labeled with "CPU XDP" on a picture. After some googling I found out that this is Intel's proprietary JTAG interface. Looking at the pinout and the differential pairs, I can clearly see the OBSFN and OBSDATA pairs on the connector on the Xeon Phi Coprocessor PCB, so this is most likely it.
Also on the other side of the board next to the power connectors is an unpopulated 3-pin connector. This is the debug UART for the NXP LPC2368 systems management controller. Nothing interesting there, it might help during reverse engineering of the SMC firmware though if anybody wants to attempt that for whatever reason.