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I am trying to compare the coherence and DRAM access cost for an application.
For this, I am thinking of measuring L3_MISS (specifically MEM_LOAD_UOPS_RETIRED.L3_MISS) events and compare it to HITM events (specifically MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM and MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM).
While looking at the description of the L3_MISS event in perfmon page (https://download.01.org/perfmon/index/) I found the following description:
Miss in last-level (L3) cache. Excludes Unknown data-source.
Based on this definition I have three questions:
1. Does the above description mean that the L3_MISS event count does not include cross-socket HITM events (since the source is _unknown_)? I couldn't find a more detailed description in the Intel SDM and the 2016 Optimization reference.
2. Speculating further, does this mean that all sub-components of L3_MISS - {LOCAL_DRAM, REMOTE_DRAM, REMOTE_FWD} are also not included in the L3_MISS count?
3. Or am I missing some definition of _unknown data source_ in the Intel SDM?
Thanks in advance!
PS: System Info - Broadwell E5 2660v4, Using PAPI to get the performance counter numbers
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