I'm working on a Broadwell xeon e5-2630 v4, trying to count stall cycles caused by L2 cache misses. In the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, volume 3, under the Broadwell-specific section, there is no mention of the A3h events, such as the CYCLE_ACTIVITY.STALLS_L2_MISS, although this event exists in both earlier (Haswell) and later (Skylake) architectures.
Is it reliable to still try and measure this event in a Broadwell machine? Or is there another way that I can monitor L2 miss stalls?
Thank you for the answer.
For earlier (4th generation) processors, the manual says to set cmask for some of the A3h events, but I see no such reference in this document. Do you think I should still set them?