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Urs_M_
Beginner
223 Views

CR0 register, CD bit

The CD bit in the CR0 register disables caches globally. I am not sure what "globally" means in this context. I guess it is one of the following:

- Disable caches on all logical processors.

- Disable caches for all memory locations on that particular logical processor? In that case: does a context switch reset this flag?

Thanks!

 

PS: Hope this is the right forum.

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3 Replies
McCalpinJohn
Black Belt
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Chapter 11 of Volume 3 of the Intel Architectures SW Developer's Manual can be challenging to interpret, since it covers many modes of operation and expects that the user will understand the existence of these modes and the occasions when they may (or must) be used.

The discussion of the control registers CR0-CR4 in Section 2.5 does not appear to mention the scope, but other sections that mention CR0 do specifically address issues of scope.  For example, Section 8.7.10 says that a MOV CR instruction (including writing to CR0) only serializes the specific logical processor that executes the instruction.  It then notes an exception to this rule -- if the write to CR0 changes the CD bit, then all logical processors associated with that physical processor are serialized.  This makes it clear that CR0.CD has a scope of "core".

I don't know if CR0 is considered part of a process context -- it looks more like a hardware control register than something that one would want to change by process context.  

I recommend a careful reading of Section 11.5.3 of Volume 3 of the Intel Arch SW Developers' Manual to get an appreciation of the complexity of dealing with CR0-based cache disabling.  

Urs_M_
Beginner
223 Views

Alright, thank you so much!

HadiBrais
New Contributor III
223 Views

The term "globally" here means that the setting applies to the whole physical address space and that it overrides all other cache control mechanisms.

Each logical core of the same physical core has its own physical CR0 register. Any defined bit of CR0 can be different in different sibling cores. However, the value of the CD flag in one sibling core may the caching behavior of all other sibling cores as described in Section 8.7.13.1 of the Intel SDM Volume 3 Revision 071:

Each logical processor has its own CR0 control register, and thus its own CD flag in CR0. The CD flags for the two logical processors are ORed together, such that when any logical processor sets its CD flag, the entire cache is nominally disabled.

On Windows and Linux, the CR0 register is a system register and not part of the process context structure. It normally doesn't change on context switches.