Cache Enabled/Disabled?

[heinerj]

Are the MTRRs, PAT, and CR0 (CD & NW) registers the only means to controling the caching of memory? Is there any other way to disable the cache? I have verified that the MTRRs type is 06 (Writeback), the PAE of all pages point to the first PATindex which is set to 06(Writeback), andwhether I set or clear the CD and NW bits of the CR0, I still get thesame performance countvalues for aL3cache miss. Myassumption is that ifthe MTRR and PAT are writeback and Iset the CD&NW bits of CR0 then all levels of cacheare disabled. But if I clear the CD & NW bits of CR0 then all levels of cache are enabled. Is this incorrect?

[Patrick_F_Intel1]

Hello heinerj,
There is no way to disable the L1, L2 or LLC.
Setting the MTTRs defines how memory references are treated.
We haven't tested the performance counters except under standard memory MTTR setup.
It has been a while since I messed with MTTRs but (if I recall correctly) if a region of memory is setup as uncacheable for instance, each load and store instruction causes a trip to memory (and can be very slow).
Does this help?
Pat

[heinerj]

If we can't disable the cache then what does the NW and CD bits of CR0 do? If the memory is setup as uncacheable either through the MTRR or the PAT does it still indicate a cache miss in the LLC?

[Patrick_F_Intel1 · Accepted solution]

You can control theuse of the cacheing using the NW & CD bits & MTRRs but the caches are not disabled.
The caches may not be used but they are not disabled.
We occassionally get questions on disabling the caches.
I assume that the uncacheable memory references will show up wither in the core counters or the uncore counters.
Pat

[rahim25]

Cache disables and enable is a big matter for anyone and you have to know how much cache you used in your hardware. The cache memory may be good for you but the memory can be disabled so that you cant use it every time. Your caches are not disabling properly and thats why you dont get the previous performance from your PC.