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Calculation of DRAM Power using MSR

Hello All, I am currently working on the performance counters. I counted different cache events using model specific registers (MSRs). I referred the following papers to use these counts for evaluating power consumption of DRAM. However, after getting event counts I am totally unaware of what to do next. I don't understand the relationship between counts and power. Let me know how to relate counts with DRAM power. Is it possible to use performance counters to estimate the DRAM power directly? Referenced papers are as follows "Complete System Power Estimation Using Processor Performance Events by Bircher, W.L. and John, L.K." "A Study on the Use of Performance Counters to Estimate Power in Microprocessors by Rodrigues, R.;Annamalai, A. ; Koren, I. ; Kundu, S."
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4 Replies
Black Belt

Recent Intel processors have a power measurement infrastructure that is described in Section 14.9 of Volume 3 of the Intel 64 and IA32 Architectures Software Developer's Manual (document 325384, revision 053, January 2015).   One of the "domains" for which energy usage estimates are provided is the DRAM domain, and the power estimates are all accessible via MSRs.

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Thanks for the quick reply.

I have gone through DRAM RAPL domain. However I am working on Intel Xeon X7350 (Intel Core micro-architecture) and it does not support the MSR_DRAM_POWER_LIMIT register. Even RAPL sub component of PAPI also does not give direct power for this architecture. 

Following is the specification of my architecture.(using cat /proc/cpuinfo),in detail.

processor    : 0
vendor_id    : GenuineIntel
cpu family    : 6
model        : 15
model name    : Intel(R) Xeon(R) CPU           X7350  @ 2.93GHz
stepping    : 11
cpu MHz        : 2933.337
cache size    : 4096 KB
physical id    : 0
siblings    : 4
core id        : 0
cpu cores    : 4
apicid        : 0
initial apicid    : 0
fpu        : yes
fpu_exception    : yes
cpuid level    : 10
wp        : yes
flags        : fpu vme de pse tsc msr pae mce cx8 apic mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall lm constant_tsc arch_perfmon pebs bts rep_good aperfmperf pni dtes64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm dca lahf_lm dts tpr_shadow vnmi flexpriority
bogomips    : 5866.86
clflush size    : 64
cache_alignment    : 64
address sizes    : 40 bits physical, 48 bits virtual
power management:

So let me know if there is any method/strategy to achieve this. As asked earlier, is it possible to use event count to estimate DRAM power?

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Hello Pramodkumar,

Your tigerton chip came out 2008 so it won't support any of the MSR based power estimations.

If I recall correctly, trying to measure the DRAM power usage is kind of tricky even with a power meter. It is hard to break out CPU power versus DRAM power. It seems like I've seen folks actually hooking up a power meter to the DRAM to properly measure its power. This was pretty involved lab work.

Another approach might be to research the DRAM type you have in the system and see if they have published power usage estimates.

I'm afraid there isn't an easy way to do what you are trying to do.



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Thank you for the valuable information.

Pramod P.

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