Confusing hardware counters

[Bo_W_4]

Hello,

i'm looking at hardware coutners of Broadwell-EP.  CYCLE_ACTIVITY_STALLS_L2_MISS and CYCLE_ACTIVITY_STALLS_L2_pending are quite similar: they are described similar (https://download.01.org/perfmon/BDW-DE/BroadwellDE_core_V5.json) and have similar values which are measured with the STREMA benchmark.

What are differences between them?

Best,

Bo

[McCalpinJohn]

In the file that you reference, these two events have the same Event code and the same Umask, so they are different names for the same event.

The only difference between the two entries (other than the names and comments) is that the CYCLE_ACTIVITY.STALLS_L2_MISS event says that it can be used on any counter when HT is off, while the CYCLE_ACTIVITY.STALLS_L2_PENDING event says that only counters 0-3 can be used when HT is off.  This may or may not be a real difference -- Intel's documentation has traditionally had some inconsistencies in this area.

[Bo_W_4]

Hello Dr. Bandwidth,

thank you. I forgot to read their Umask and Event code. Only, their are descriped differently, i thought they are differnt.

Best,

Bo