Hi, i have some small questions about cache descriptors (tlb), my processor is an i3-ivy bridge:
1 - What would be number 0 and 1 after dtlb?
2 - In the instructions section, in cpuid, has a descriptor named as 'uTLB', although it looks like a Tlb of data in level 1, what does this mean?
3 - A descriptor in the instructions section, in cpuid, does not say what would be its associativity, although it seems to be full.
4 - some descriptors use '/' as a separator of page size, this makes it appear that in cases it means 'AND' in others 'OR', I would like to have this ambiguity resolved.
Ex: 2MB / 4MB is impossible '/' to mean 'AND' in cpu mode of operation(PAE, legacy PAE) although in some descriptors the meaning of '/' is undefined.
5 - What would be the caches with sectorized lines?