DMA synchronisation with incoming MWr-TLP

Software Tuning, Performance Optimization & Platform Monitoring

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DMA synchronisation with incoming MWr-TLP

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Hello Intel-Forum,

The hardware is a i7-4770S with a board plugged into the x16 PCIe slot. The board is sending a Memory-Write TLP over the PCIe bus to the root complex. This root complex is the i7 die. The only documentation I could find about the further processing of the TLP is the Core2-documentation.

By this documentation I very much assume that one of the next stations for the data is the DMA control unit. Is this assumption right?

This unit will deal with the data and make it available for CPU-directives. I still have to figure out on which address the data will be available, but this can be OS specific. As far as I have heard will be the address in the TLP an offset to a dedicated memory.(Thanks in advance for any hint on this...)

Is it possible to subscribe to a synchronisation trigger from the DMA unit, e.g. an interrupt, to wake up when the data are accessible?

regards

AppleCake

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