Software Tuning, Performance Optimization & Platform Monitoring
Discussion regarding monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, and platform updating.
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
1790 Discussions

DMA synchronisation with incoming MWr-TLP

Pay_S_
Beginner
‎02-08-2016 06:55 AM
641 Views

Hello Intel-Forum,

The hardware is a i7-4770S with a board plugged into the x16 PCIe slot. The board is sending a Memory-Write TLP over the PCIe bus to the root complex. This root complex is the i7 die. The only documentation I could find about the further processing of the TLP is the Core2-documentation.

By this documentation I very much assume that one of the next stations for the data is the DMA control unit. Is this assumption right?

This unit will deal with the data and make it available for CPU-directives. I still have to figure out on which address the data will be available, but this can be OS specific. As far as I have heard will be the address in the TLP an offset to a dedicated memory.(Thanks in advance for any hint on this...)

Is it possible to subscribe to a synchronisation trigger from the DMA unit, e.g. an interrupt, to wake up when the data are accessible?

 

regards

AppleCake

 

0 Kudos

Link Copied

0 Replies
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.