Description of DRAM Refresh Unit Masks?

[Nash_R_]

Hi, 

I'm wondering what the difference is between the unit masks for Panic and High refreshes listed in the E5-2600 Product Family Uncore Performance Montior guide (page 66). Quantitiatively, the mask for "panic" seems to give me refresh results in line with my expectations, given the specifications for the specific part I'm using. What sort of events is the "high" umask counting, anyway? The values I'm getting for the "high" umask are at least two orders of magnitude larger than the "panic" umask when the system is sitting idle (200,000-600,000 for high while 500-6,000 for panic).

Thank you!

Nash Reilly

[Bernard]

I looked at the exact explanation on the page 66 and it is unclear what panic and high umask exactly mean.I think that these settings could measure frequency or rate of DRAM refresh cycles.

[Nash_R_]

Yeah, I didn't fail to RTFM on this one. :D 

Some of the values I'm getting on Panic refresh also don't seem to make sense. I'm doing a simple test on the memory that John McCalpin provided source code for on his blog (writing to an array larger than cache size), and the refresh values drop to zero even though the test period is about the same length as the device refresh period; there absolutely should be a refresh on each cell in that time. Neither Panic, High, nor Power-Self Refresh monitors yield any appreciable insight onto refresh values. 

[Bernard]

Do you use Stream benchmark?Btw John's blog is very interesting and insightful. DRAM refreshes are performed with the frequency of one refresh per 64 miliseconds.So the interval of refreshes will be refresh time / number of rows = 7.8 us.Maybe your code runs faster that refresh interval?How do you measure DRAM_REFRESH interval?.

[Nash_R_]

iliyapolak wrote:

DRAM refreshes are performed with the frequency of one refresh per 64 miliseconds.So the interval of refreshes will be refresh time / number of rows = 7.8 us.Maybe your code runs faster that refresh interval?How do you measure DRAM_REFRESH interval?.

I'm writing an array that takes ~27 million clock cycles  to complete, or (2.7e7 * 1.25e-9 s = )  0.03375 s. There should be a few refreshes issued in that timeframe. 

[Bernard]

It seems that your values for high umask(200,000-600,000 ) and at least its lower range could be correct.It is unknown for me what is the source of the deviation.Panic umask values simply do not make sense.It seems that they are calculated by dividing refresh time by the some number of rows whuich is less than the calculation of High umask.

[Nash_R_]

iliyapolak wrote:

It seems that your values for high umask(200,000-600,000 ) and at least its lower range could be correct.It is unknown for me what is the source of the deviation.Panic umask values simply do not make sense.It seems that they are calculated by dividing refresh time by the some number of rows whuich is less than the calculation of High umask.

Sorry, I keep failing to state my assumptions on this: I wrote a simple C++ program that loops forever, sampling our perfmon counters every 64 ms. I've been able to confirm with a logic analyzer that the values for the "panic" setting are the most accurate; I've done some testing with power regulation enabled and disabled in the system BIOS as well to verify. For the system I'm using, "panic" seems to be the mask that grabs refreshes for when the memory module isn't in a powerdown state, and power_self_refresh grabs the number of clock cycles that the module spends just being self-refreshed to maintain data. I'm trying to figure out what the "high" setting is measuring, because I can't seem to correlate those to any sort of real value I've measured with the logic analyzer.

[Bernard]

I do not know what exactly High umask could be used for.By inspecting your data related to High umask bitfield I came to conclusion that this mask can measure(count) the total number of refreshes as function of refresh interval which is 7.8 microsec.