Software Tuning, Performance Optimization & Platform Monitoring
Discussion regarding monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, and platform updating.
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.

Details on the RAPLModel

Ronny_B_
Beginner
803 Views

Hey,

is the model RAPL uses publicy available?

Or did by any chance someone reverse engineer it?

I'd be very interested to use it to predict power consumption of algorithms.

cheers,

Ronny

0 Kudos
3 Replies
Patrick_F_Intel1
Employee
803 Views

Hello Ronny,

The only information that Intel has exposed is in the "Intel® 64 and IA-32 Architectures Software Developer’s Manual", Volume 3 (3A, 3B & 3C), System Programming Guide available http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html.

See section 14.7 "PLATFORM SPECIFIC POWER MANAGEMENT SUPPORT", page 14-19, March 2013 edition.

Pat

0 Kudos
Ronny_B_
Beginner
804 Views

that and this http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5599016&tag=1

but, sadly, I didn't find anything else.

0 Kudos
Bernard
Valued Contributor I
804 Views

Ronny B. wrote:

Hey,

is the model RAPL uses publicy available?

Or did by any chance someone reverse engineer it?

I'd be very interested to use it to predict power consumption of algorithms.

cheers,

Ronny

How it could be reverse engineered? I suppose that an exact implementation is at microcode/hardware/ACPI level.

0 Kudos
Reply