The discussion in Section 14.9 of Volume 3 of the Intel Architecture SW Developer's Manual (document 325384) mentions the locking capability of the MSR_PKG_POWER_LIMIT register. The wording is not as clear as I would like -- the document says "Once the lock bit is set, the power limit settings are static and un-modifiable until next RESET." It is not clear whether the locking mechanism applies to every bit in the register or just the four fields that have "power limit" in their names.
In any case, the ability to change the clamping enable bits but not the limit enable bits suggests that there is another level of control -- probably in the BIOS. Unfortunately, documentation about the hardware configuration options used by the BIOS is quite limited. Many (most?) of the settings controlled by the BIOS can only be seen or modified in SMM mode anyway, so unless you have the ability to modify the BIOS there is not much point in knowing about the options.
